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ORCIDSyed Ershad Ahmed
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2020 – today
- 2024
[j14]Aditya Anirudh Jonnalagadda
, Uppugunduru Anil Kumar, Rishi Thotli, Satvik Sardesai, Sreehari Veeramachaneni, Syed Ershad Ahmed:
ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks. IEEE Access 12: 31036-31046 (2024)- [j13]Aalelai Vendhan, Syed Ershad Ahmed, S. Gurunarayanan:
Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders. Circuits Syst. Signal Process. 43(7): 4050-4072 (2024) - [c19]Rishi Agrawal, Narayanabhatla Savyasachi Abhijith, Uppugunduru Anil Kumar, Sreehari Veeramachaneni, Syed Ershad Ahmed:
Energy-Efficient Ternary Multiplier. AICAS 2024: 382-387 - 2023
- [j12]Sahith Guturu, Uppugunduru Anil Kumar, S. Vignesh Bharadwaj, Syed Ershad Ahmed:
Design methodology for highly accurate approximate multipliers for error resilient applications. Comput. Electr. Eng. 110: 108798 (2023) - [j11]Uppugunduru Anil Kumar, S. Vignesh Bharadwaj, Avinash Bhat Pattaje, Suresh Nambi, Syed Ershad Ahmed:
CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications. IEEE Embed. Syst. Lett. 15(3): 117-120 (2023) - [j10]Aroondhati Bhure, P. Smriti, Vinay Dhanote, Uppugunduru Anil Kumar, Syed Ershad Ahmed:
A General Methodology to Optimize Flagged Constant Addition. J. Circuits Syst. Comput. 32(2): 2350027:1-2350027:16 (2023) - [j9]Pramod Alamuri, Uppugunduru Anil Kumar, Vallepu Vannuru, Syed Ershad Ahmed:
Improved approximate multiplier architecture for image processing and neural network applications. Microprocess. Microsystems 101: 104909 (2023) - [c18]Aditya Anirudh Jonnalagadda, Anil Kumar Uppugunduru, Sreehari Veeramachaneni, Syed Ershad Ahmed:
Design of Energy Efficient Posit Multiplier. ACM Great Lakes Symposium on VLSI 2023: 645-651 - [c17]Sangireddy Tharuni, Basani Harshavardhan Reddy, Bhukya Mamatha, Uppugunduru Anil Kumar, Syed Ershad Ahmed, Sreehari Veeramachaneni:
Power Efficient Approximate Ternary Subtractor for Image Processing Applications. iSES 2023: 127-130 - 2022
- [j8]Anil Kumar Uppugunduru, S. Vignesh Bharadwaj, Syed Ershad Ahmed:
Compressor based hybrid approximate multiplier architectures with efficient error correction logic. Comput. Electr. Eng. 104(Part): 108407 (2022) - [j7]Uppugunduru Anil Kumar, Sumit K. Chatterjee, Syed Ershad Ahmed:
Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module. IEEE Embed. Syst. Lett. 14(2): 59-62 (2022) - [j6]Uppugunduru Anil Kumar, G. Sahith, Sumit K. Chatterjee, Syed Ershad Ahmed:
A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications. J. Circuits Syst. Comput. 31(3): 2250049:1-2250049:17 (2022) - [j5]Uppugunduru Anil Kumar, Sahith Guturu, Syed Ershad Ahmed:
Design and exploration of low-power SAD architectures using approximate compressors for Integer Motion Estimation. Microprocess. Microsystems 94: 104659 (2022) - 2021
- [j4]Suresh Nambi, Uppugunduru Anil Kumar, Kavya Radhakrishnan, Mythreye Venkatesan, Syed Ershad Ahmed:
DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications. IEEE Embed. Syst. Lett. 13(4): 174-177 (2021) - [j3]Syed Ershad Ahmed, Yerasuri Mohana Sri Krishna:
An Efficient Hardware Approach for Approximate Logarithmic Computation. J. Circuits Syst. Comput. 30(9): 2150165:1-2150165:18 (2021) - [c16]Sahith Guturu, Anil Kumar Uppugunduru, Sridhar Thota, Syed Ershad Ahmed:
Power-Efficient MLOA for error resilient applications. iSES 2021: 79-83 - [c15]Uppugunduru Anil Kumar, Ratna Kumari Chintakunta, Sandeep Kumar, K. Jamal, Syed Ershad Ahmed:
Approximate Multiplier Architectures for Error Resilient Applications. iSES 2021: 89-92 - [c14]Uppugunduru Anil Kumar, Goli Naga Sandesh, Dhoti Ojusteja, Syed Ershad Ahmed:
Lower part OR based Approximate Multiplier for Error Resilient Applications. iSES 2021: 161-164 - 2020
- [c13]Uppugunduru Anil Kumar, Nishant Jain, Sumit K. Chatterjee, Syed Ershad Ahmed:
Evaluation of Multiplier-Less DCT Transform Using In-Exact Computing. MIND (2) 2020: 11-23
2010 – 2019
- 2019
- [j2]Syed Ershad Ahmed, M. B. Srinivas:
An Improved Logarithmic Multiplier for Media Processing. J. Signal Process. Syst. 91(6): 561-574 (2019) - 2018
- [j1]Syed Ershad Ahmed, Ch. Santosh Varma, M. B. Srinivas:
Improved designs of digit-by-digit decimal multiplier. Integr. 61: 150-159 (2018) - 2016
- [c12]Syed Ershad Ahmed, Sanket Kadam, M. B. Srinivas:
An Iterative Logarithmic Multiplier with Improved Precision. ARITH 2016: 104-111 - [c11]Syed Ershad Ahmed, S. Sweekruth Srinivas, M. B. Srinivas:
A Hybrid Energy Efficient Digital Comparator. VLSID 2016: 567-568 - 2014
- [c10]Soumya Ganguly, Abhishek Mittal, Syed Ershad Ahmed, M. B. Srinivas:
A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits. APCCAS 2014: 69-72 - [c9]Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas:
A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter. VLSID 2014: 365-368 - 2012
- [c8]Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Modified Twin Precision Multiplier with 2D Bypassing Technique. ISED 2012: 102-106 - [c7]Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas:
Design of Prefix-Based Optimal Reversible Comparator. ISVLSI 2012: 201-206 - [c6]Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas:
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. ISVLSI 2012: 225-230 - [c5]Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design 2012: 280-285 - 2011
- [c4]Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Unified Architecture for BCD and Binary Adder/Subtractor. DSD 2011: 426-429 - [c3]P. Sai Phaneendra, Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. ISCIT 2011: 472-477 - [c2]Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. ISED 2011: 100-105 - [c1]Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Prefix Based Reconfigurable Adder. ISVLSI 2011: 349-350
Coauthor Index
aka: Anil Kumar Uppugunduru
aka: Mandalika B. Srinivas
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