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2020 – today
- 2024
[j21]Wan-Ling Wu, Jen-Wei Hsieh
, Hao-Yu Ku:
CDS: Coupled Data Storage to Enhance Read Performance of 3D TLC NAND Flash Memory. IEEE Trans. Computers 73(3): 694-707 (2024)- [c28]Han-Yu Liao, Wen-Ling Hsu, Jen-Wei Hsieh, Hung-Pin Chen:
Read Retry Mechanism for 3D NAND Flash Memory: Observations, Analyses, and Solutions. NVMSA 2024: 1-6 - 2023
- [c27]Yi-Shen Chen, Ying-Jui Shih, Jen-Wei Hsieh:
Mitigating Write Amplification of Dual-mode Flash Memory. ISOCC 2023: 243-244 - 2022
- [j20]Tai Chang, Jen-Wei Hsieh, Tai-Chieh Chang, Liang-Wei Lai:
EMT: Elegantly Measured Tanner for Key-Value Store on SSD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 91-103 (2022) - [j19]Jen-Wei Hsieh, Yueh-Ting Hou, Tai-Chieh Chang:
Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM Cache. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2753-2757 (2022) - [j18]David Kuang-Hui Yu, Jen-Wei Hsieh:
Differential Evolution Algorithm With Asymmetric Coding for Solving the Reliability Problem of 3D-TLC CT Flash-Memory Storage Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2863-2876 (2022) - [c26]Chih-Chia Chen, Jen-Wei Hsieh:
Nimble Mapping SSD: Leaning State Mapping Strategy to Increase Reliability of 3D TLC Charge-Trap NAND Flash Memory. NVMSA 2022: 57-62 - 2021
- [j17]Jen-Wei Hsieh, Yi-Yu Liu, Hung-Tse Lee, Tai Chang:
TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache. IEEE Trans. Computers 70(9): 1498-1510 (2021) - [c25]Yao-Hung Huang, Jen-Wei Hsieh:
Read/Write Disturbance-Aware Design for MLC STT-RAM-based Cache. RTCSA 2021: 11-20 - 2020
- [j16]David Kuang-Hui Yu, Jen-Wei Hsieh:
A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage Devices. IEEE Trans. Computers 69(4): 549-562 (2020) - [c24]Ping Cheng, Jen-Wei Hsieh:
Early eviction and swapping for MLC STT-RAM-based LLC. SAC 2020: 590-592
2010 – 2019
- 2019
- [j15]Han-Yi Lin, Jen-Wei Hsieh:
Revive Bad Flash-Memory Pages by HLC Scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 860-873 (2019) - [j14]Luís Almeida, Björn Andersson, Jen-Wei Hsieh, Li-Pin Chang, Xiaobo Sharon Hu:
Introduction to the Special Issue on Real-Time aspects in Cyber-Physical Systems. ACM Trans. Cyber Phys. Syst. 3(3): 24:1-24:2 (2019) - 2018
- [c23]Nguyen-Van Hiep, Jen-Wei Hsieh:
Timestamp-based hot/cold data identification scheme for solid state drives. RACS 2018: 255-259 - [c22]David Kuang-Hui Yu, Jen-Wei Hsieh:
Retention-Time Relaxation Scheme for MLC Flash-Memory Storage Systems. RTCSA 2018: 42-51 - 2016
- [c21]Jen-Wei Hsieh, Che-Jen Su:
Parity management scheme for a hybrid-storage RAID. SAC 2016: 1774-1776 - 2015
- [j13]Jiantao Wang, Kam-yiu Lam, Yuan-Hao Chang, Jen-Wei Hsieh, Po-Chun Huang:
Block-Based Multi-Version B+-Tree for Flash-Based Embedded Database Systems. IEEE Trans. Computers 64(4): 925-940 (2015) - [j12]Jen-Wei Hsieh, Yuan-Hung Kuan:
DCCS: Double Circular Caching Scheme for DRAM/PRAM Hybrid Cache. IEEE Trans. Computers 64(11): 3115-3127 (2015) - [j11]Jen-Wei Hsieh, Chung-Wei Chen, Han-Yi Lin:
Adaptive ECC Scheme for Hybrid SSD's. IEEE Trans. Computers 64(12): 3348-3361 (2015) - [c20]Han-Yi Lin, Jen-Wei Hsieh:
HLC: software-based half-level-cell flash memory. DATE 2015: 936-941 - 2014
- [j10]Kam-yiu Lam, Chun Jiang Zhu, Yuan-Hao Chang, Jen-Wei Hsieh, Po-Chun Huang, Chung Keung Poon, Jiantao Wang:
Garbage collection of multi-version indexed data on flash memory. J. Syst. Archit. 60(8): 630-643 (2014) - [j9]Jen-Wei Hsieh, Han-Yi Lin, Dong-Lin Yang:
Multi-Channel Architecture-Based FTL for Reliable and High-Performance SSD. IEEE Trans. Computers 63(12): 3079-3091 (2014) - [c19]Kam-yiu Lam, Jiantao Wang, Yuan-Hao Chang, Jen-Wei Hsieh, Po-Chun Huang, Chung Keung Poon, Chun Jiang Zhu:
Garbage collection for multi-version index on flash memory. DATE 2014: 1-4 - [c18]Jen-Wei Hsieh, Ming-Xian Liu:
Configurable reliability framework for SSD-RAID. NVMSA 2014: 1-6 - 2013
- [j8]Jen-Wei Hsieh, Yu-Cheng Zheng, Yong-Sheng Peng, Po-Hung Yeh:
VAST: Virtually Associative Sector Translation for MLC Storage Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1137-1150 (2013) - [j7]Jen-Wei Hsieh, Yuan-Hao Chang, Yuan-Sheng Chu:
Implementation strategy for downgraded flash-memory storage devices. ACM Trans. Embed. Comput. Syst. 12(1s): 60:1-60:29 (2013) - 2012
- [j6]Jen-Wei Hsieh, Chung-Hsien Wu, Ge-Ming Chiu:
MFTL: A Design and Implementation for MLC Flash Memory Storage Systems. ACM Trans. Storage 8(2): 7:1-7:29 (2012) - [c17]Jen-Wei Hsieh, Yuan-Hung Kuan:
Double Circular Caching Scheme for DRAM/PRAM Hybrid Cache. RTCSA 2012: 469-472 - 2011
- [c16]Jen-Wei Hsieh, Yuan-Hao Chang, Wei-Li Lee:
An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs. ASP-DAC 2011: 661-667 - [c15]Chun-Chieh Kuo, Jen-Wei Hsieh, Li-Pin Chang:
Detecting Solid-State Disk Geometry for Write Pattern Optimization. RTCSA (2) 2011: 89-94 - [c14]Jen-Wei Hsieh, Shang-Yang Chang:
An open-system framework for flash-memory storage system. SAC 2011: 605-610 - 2010
- [j5]Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo:
Improving Flash Wear-Leveling by Proactively Moving Static Data. IEEE Trans. Computers 59(1): 53-65 (2010) - [j4]Yuan-Hao Chang, Jian-Hong Lin, Jen-Wei Hsieh, Tei-Wei Kuo:
A strategy to emulate NOR flash with NAND flash. ACM Trans. Storage 6(2): 5:1-5:23 (2010) - [c13]Jen-Wei Hsieh, Chung-Hsien Wu, Ge-Ming Chiu:
Design and Implementation for Multi-level Cell Flash Memory Storage Systems. RTCSA 2010: 247-252
2000 – 2009
- 2009
- [c12]Yuan-Sheng Chu, Jen-Wei Hsieh, Yuan-Hao Chang, Tei-Wei Kuo:
A set-based mapping strategy for flash-memory reliability enhancement. DATE 2009: 405-410 - 2008
- [j3]Jen-Wei Hsieh, Yi-Lin Tsai, Tei-Wei Kuo, Tzao-Lin Lee:
Configurable Flash-Memory Management: Performance versus Overheads. IEEE Trans. Computers 57(11): 1571-1583 (2008) - [c11]Po-Chun Huang, Yuan-Hao Chang, Tei-Wei Kuo, Jen-Wei Hsieh, Miller Lin:
The Behavior Analysis of Flash-Memory Storage Systems. ISORC 2008: 529-534 - 2007
- [c10]Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo:
Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design. DAC 2007: 212-217 - [c9]Jen-Wei Hsieh, Tei-Wei Kuo, Po-Liang Wu, Yu-Chung Huang:
Energy-efficient and performance-enhanced disks using flash-memory cache. ISLPED 2007: 334-339 - [c8]Jian-Hong Lin, Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, Cheng-Chih Yang:
A NOR Emulation Strategy over NAND Flash Memory. RTCSA 2007: 95-102 - 2006
- [j2]Wan-Chen Lu, Jen-Wei Hsieh, Wei-Kuan Shih, Tei-Wei Kuo:
A faster exact schedulability analysis for fixed-priority scheduling. J. Syst. Softw. 79(12): 1744-1753 (2006) - [j1]Jen-Wei Hsieh, Tei-Wei Kuo, Li-Pin Chang:
Efficient identification of hot data for flash memory storage systems. ACM Trans. Storage 2(1): 22-40 (2006) - [c7]Tei-Wei Kuo, Jen-Wei Hsieh, Li-Pin Chang, Yuan-Hao Chang:
Configurability of performance and overheads in flash management. ASP-DAC 2006: 334-341 - [c6]Wan-Chen Lu, Jen-Wei Hsieh, Wei-Kuan Shih:
A precise schedulability test algorithm for scheduling periodic tasks in real-time systems. SAC 2006: 1451-1455 - [c5]Yi-Lin Tsai, Jen-Wei Hsieh, Tei-Wei Kuo:
Configurable NAND Flash Translation Layer. SUTC (1) 2006: 118-127 - 2005
- [c4]Jen-Wei Hsieh, Li-Pin Chang, Tei-Wei Kuo:
Efficient on-line identification of hot data for flash-memory management. SAC 2005: 838-842 - 2003
- [c3]Jen-Wei Hsieh, Guo-Ruey Tsai, Min-Chuan Lin:
Using FPGA to implement a n-channel arbitrary waveform generator with various add-on functions. FPT 2003: 296-298 - [c2]Nei-Chiung Perng, Neung-Tsung Tsai, Jen-Wei Hsieh, Tei-Wei Kuo:
The Design and Implementation of A Real-Time Data Dispatching System. ISORC 2003: 285-291 - [c1]Chung-You Wei, Jen-Wei Hsieh, Tei-Wei Kuo, I-Hsiang Lee, Yian-Nien Wu, Mei-Chin Tsa:
Resource Reservation and Enforcement for Framebuffer-Based Devices. RTCSA 2003: 398-408
Coauthor Index
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