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Je-Ching Liu

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2010 – 2019

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2010
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Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang:
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. IEEE J. Solid State Circuits 45(5): 1036-1047 (2010)
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Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang:
A 55nm 1GHz one-cycle-locking de-skewing circuit. ISCAS 2010: 1755-1758

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