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2020 – today
- 2022
[j33]Boyang Du
, Sarah Azimi, Annarita Moramarco, Davide Sabena, Filippo Parisi, Luca Sterpone:
An Automated Continuous Integration Multitest Platform for Automotive Systems. IEEE Syst. J. 16(2): 2495-2506 (2022)- [j32]Corrado De Sio, Sarah Azimi, Luca Sterpone:
FireNN: Neural Networks Reliability Evaluation on Hybrid Platforms. IEEE Trans. Emerg. Top. Comput. 10(2): 549-563 (2022) - [j31]Marcio M. Gonçalves, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone, José Rodrigo Azambuja:
Evaluating low-level software-based hardening techniques for configurable GPU architectures. J. Supercomput. 78(6): 8081-8105 (2022) - [e1]Luca Sterpone, Andrea Bartolini, Anastasiia Butko:
CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17 - 22, 2022. ACM 2022, ISBN 978-1-4503-9338-6 [contents] - 2021
- [j30]Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone:
DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability. J. Supercomput. 77(10): 11625-11642 (2021) - [j29]Sarah Azimi, Corrado De Sio, Luca Sterpone:
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication. IEEE Trans. Very Large Scale Integr. Syst. 29(8): 1596-1600 (2021) - [c115]Sarah Azimi, Corrado De Sio, Luca Sterpone:
A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor. DATE 2021: 252-257 - [c114]Corrado De Sio, Sarah Azimi, Andrea Portaluri, Luca Sterpone:
SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft Processor. DFT 2021: 1-6 - [c113]Ludovica Bozzoli, Corrado De Sio, Boyang Du, Luca Sterpone:
A Neutron Generator Testing Platform for the Radiation Analysis of SRAM-based FPGAs. I2MTC 2021: 1-5 - [c112]Andrea Portaluri, Corrado De Sio, Sarah Azimi, Luca Sterpone:
A New Domains-based Isolation Design Flow for Reconfigurable SoCs. IOLTS 2021: 1-7 - [c111]Sarah Azimi, Corrado De Sio, Luca Sterpone:
On the Evaluation of SEEs on Open-Source Embedded Static RAMs. VLSI-SoC 2021: 1-6 - 2020
- [j28]Ludovica Bozzoli, Luca Sterpone:
An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs. IEEE Access 8: 116226-116238 (2020) - [c110]Ludovica Bozzoli, Luca Sterpone:
Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs. ARC 2020: 84-96 - [c109]Corrado De Sio, Sarah Azimi, Luca Sterpone:
On the Evaluation of SEU Effects on AXI Interconnect Within AP-SoCs. ARCS 2020: 215-227 - [c108]Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka:
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE 2020: 388-393 - [c107]Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone:
A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs. DDECS 2020: 1-6 - [c106]Corrado De Sio, Sarah Azimi, Luca Sterpone:
An Emulation Platform for Evaluating the Reliability of Deep Neural Networks. DFT 2020: 1-4 - [c105]Sarah Azimi, Corrado De Sio, Luca Sterpone:
In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops. IOLTS 2020: 1-6 - [c104]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. IOLTS 2020: 1-7 - [c103]Josie E. Rodriguez Condia, Marcio Gonçalves, José Rodrigo Azambuja, Matteo Sonza Reorda, Luca Sterpone:
Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets. ISVLSI 2020: 380-385 - [c102]Sarah Azimi, Luca Sterpone:
Digital Design Techniques for Dependable High Performance Computing. ITC 2020: 1-10 - [c101]Marcio Gonçalves, José Rodrigo Azambuja, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone:
Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU. LATS 2020: 1-6 - [c100]Sarah Azimi, Corrado De Sio, Weitao Yang, Luca Sterpone:
A New Single Event Transient Hardened Floating Gate Configurable Logic Circuit. NEWCAS 2020: 311-314 - [c99]Josie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone:
A dynamic reconfiguration mechanism to increase the reliability of GPGPUs. VTS 2020: 1-6 - [i6]Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks. CoRR abs/2002.05455 (2020) - [i5]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits. CoRR abs/2002.08882 (2020) - [i4]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques. CoRR abs/2002.09945 (2020) - [i3]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features. CoRR abs/2008.13664 (2020)
2010 – 2019
- 2019
- [j27]Corrado De Sio, Sarah Azimi, Luca Sterpone, Boyang Du:
Analyzing Radiation-Induced Transient Errors on SRAM-Based FPGAs by Propagation of Broadening Effect. IEEE Access 7: 140182-140189 (2019) - [j26]Sarah Azimi, Boyang Du, Luca Sterpone, David Merodio Codinachs, Raoul Grimoldi, L. Cattaneo:
A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs. Integr. 67: 73-81 (2019) - [c98]Ludovica Bozzoli, Luca Sterpone:
ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures. ARC 2019: 295-304 - [c97]Sergei Odintsov, Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Artur Jutman:
A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network. DDECS 2019: 1-6 - [c96]Boyang Du, Sarah Azimi, Corrado De Sio, Ludovica Bozzoli, Luca Sterpone:
On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGA. DFT 2019: 1-6 - [c95]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques. DSN (Supplements) 2019: 35-41 - [c94]Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks. DTIS 2019: 1-6 - [c93]Corrado De Sio, Sarah Azimi, Luca Sterpone:
On the Evaluation of the PIPB Effect within SRAM-based FPGAs. ETS 2019: 1-2 - [c92]Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone:
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits. IOLTS 2019: 7-14 - [c91]Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone:
On the evaluation of SEU effects in GPGPUs. LATS 2019: 1-6 - [c90]Luca Sterpone, Ludovica Bozzoli, Corrado De Sio, Boyang Du, Sarah Azimi:
A new Method for the Analysis of Radiation-induced Effects in 3D VLSI Face-to-Back LUTs. SMACD 2019: 205-208 - [i2]Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka:
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR abs/1912.01561 (2019) - 2018
- [j25]Sarah Azimi, Luca Sterpone, Boyang Du, Luca Boragno:
On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs. Microelectron. Reliab. 88-90: 936-940 (2018) - [j24]Dario Cozzi, Sebastian Korf, Luca Cassano, Jens Hagemeyer, Andrea Domenici, Cinzia Bernardeschi, Luca Sterpone, Mario Porrmann:
OLT(RE)2: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems. IEEE Trans. Emerg. Top. Comput. 6(4): 511-523 (2018) - [c89]Luca Sterpone, Sarah Azimi, Ludovica Bozzoli, Boyang Du, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Cesar Boatella Polo, David Merodio Codinachs:
A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs. AHS 2018: 120-126 - [c88]Luca Sterpone, Ludovica Bozzoli:
Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach. ARC 2018: 319-330 - [c87]Ludovica Bozzoli, Luca Sterpone:
MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories. DFT 2018: 1-6 - [c86]Sarah Azimi, Boyang Du, Luca Sterpone:
On the mitigation of single event transients on flash-based FPGAs. ETS 2018: 1-2 - [c85]Boyang Du, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Luca Sterpone:
About the functional test of the GPGPU scheduler. IOLTS 2018: 85-90 - [c84]Ludovica Bozzoli, Luca Sterpone:
IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs. ISCAS 2018: 1-5 - [c83]Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Cinzia Bernardeschi:
PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing. RSP 2018: 70-75 - [c82]Sarah Azimi, Boyang Du, Luca Sterpone, David Merodio Codinachs, L. Cattaneo:
SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs. SMACD 2018: 1-52 - 2017
- [j23]Sarah Azimi, Boyang Du, Luca Sterpone:
Evaluation of transient errors in GPGPUs for safety critical applications: An effective simulation-based fault injection environment. J. Syst. Archit. 75: 95-106 (2017) - [j22]Luis Andres Cardona, Anees Ullah, Luca Sterpone, Carles Ferrer:
A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs. J. Syst. Archit. 81: 112-120 (2017) - [j21]Anees Ullah, Ernesto Sánchez, Luca Sterpone, Luis Andres Cardona, Carles Ferrer:
An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs. Microelectron. Reliab. 75: 110-120 (2017) - [j20]Qiutao Zhang, Sarah Azimi, Germano La Vaccara, Luca Sterpone, Boyang Du:
A new approach for Total Ionizing Dose effect analysis on Flash-based FPGA. Microelectron. Reliab. 76-77: 58-63 (2017) - [j19]Luca Sterpone, Luca Boragno:
A probe-based SEU detection method for SRAM-based FPGAs. Microelectron. Reliab. 76-77: 154-158 (2017) - [j18]Matteo Sonza Reorda, Luca Sterpone, Anees Ullah:
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems. IEEE Trans. Computers 66(6): 1022-1033 (2017) - [c81]Ludovica Bozzoli, Luca Sterpone:
Self rerouting of dynamically reconfigurable SRAM-based FPGAs. AHS 2017: 77-84 - [c80]Luca Sterpone, Sarah Azimi, Boyang Du, David Merodio Codinachs, Raoul Grimoldi:
Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs. ACM Great Lakes Symposium on VLSI 2017: 203-208 - [c79]Boyang Du, Luca Sterpone:
Online monitoring soft errors in reconfigurable FPGA during radiation test. I2MTC 2017: 1-5 - [c78]Luca Sterpone, Luca Boragno:
Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs. IOLTS 2017: 174-179 - [c77]Sarah Azimi, Annarita Moramarco, Luca Sterpone:
Reliability evaluation of heterogeneous systems-on-chip for automotive ECUs. ISIE 2017: 1291-1296 - [c76]Sarah Azimi, Luca Sterpone:
Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach. ISVLSI 2017: 338-343 - [c75]Boyang Du, Luca Sterpone:
Fault tolerant electronic system design. ITC 2017: 1-6 - 2016
- [j17]Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone:
UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs. Integr. 55: 85-97 (2016) - [j16]Sarah Azimi, Boyang Du, Luca Sterpone:
On the prediction of radiation-induced SETs in flash-based FPGAs. Microelectron. Reliab. 64: 230-234 (2016) - [j15]Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena:
Online Test of Control Flow Errors: A New Debug Interface-Based Approach. IEEE Trans. Computers 65(6): 1846-1855 (2016) - [c74]Sarah Azimi, Boyang Du, Luca Sterpone:
A New Simulation-Based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs. ARCS 2016: 388-400 - [c73]Boyang Du, Luca Sterpone, David Merodio Codinachs:
A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs. ETS 2016: 1-2 - [c72]Luca Sterpone, Gianpiero Cabodi, Sebastiano F. Finocchiaro, Carmelo Loiacono, Francesco Savarese, Boyang Du:
Scalable FPGA graph model to detect routing faults. IOLTS 2016: 155-160 - [c71]Eduardo Chielle, Boyang Du, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi, Luca Sterpone, Matteo Sonza Reorda:
Hybrid soft error mitigation techniques for COTS processor-based systems. LATS 2016: 99-104 - [c70]Luca Sterpone, Luca Boragno, David Merodio Codinachs:
Analysis of radiation-induced SEUs on dynamic reconfigurable systems. ReCoSoC 2016: 1-6 - [c69]Boyang Du, Luca Sterpone:
An FPGA-based testing platform for the validation of automotive powertrain ECU. VLSI-SoC 2016: 1-7 - 2015
- [j14]Luca Sterpone, Boyang Du, Sarah Azimi:
Radiation-induced single event transients modeling and testing on nanometric flash-based technologies. Microelectron. Reliab. 55(9-10): 2087-2091 (2015) - [c68]Luca Sterpone, Boyang Du:
SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs. ARC 2015: 129-140 - [c67]Boyang Du, Luca Sterpone, Lorenzo Venditti, David Merodio Codinachs:
On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs. ReCoSoC 2015: 1-6 - 2014
- [j13]Anees Ullah, Luca Sterpone:
Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs. J. Electron. Test. 30(4): 425-442 (2014) - [j12]Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro:
Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results. Microelectron. Reliab. 54(11): 2621-2628 (2014) - [j11]Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone:
ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1342-1355 (2014) - [j10]Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 813-823 (2014) - [c66]Dan Alexandrescu, Luca Sterpone, Celia López-Ongil:
Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation. ETS 2014: 1-6 - [c65]Davide Sabena, Luca Sterpone, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus, S. Wong, Robért Glein, Florian Rittner, C. Stender, Mario Porrmann, Jens Hagemeyer:
Reconfigurable high performance architectures: How much are they ready for safety-critical applications? ETS 2014: 1-8 - [c64]Luca Sterpone, Boyang Du:
Analysis and mitigation of single event effects on flash-based FPGAS. ETS 2014: 1-6 - [c63]Ernesto Sánchez, Luca Sterpone, Anees Ullah:
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. FPL 2014: 1-6 - [c62]Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena:
A new solution to on-line detection of Control Flow Errors. IOLTS 2014: 105-110 - [c61]Marco Desogus, Luca Sterpone, David Merodio Codinachs:
Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs. IOLTS 2014: 111-115 - [c60]M. De Carvalho, Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro:
Fault injection in GPGPU cores to validate and debug robust parallel applications. IOLTS 2014: 210-211 - [c59]Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
Soft error effects analysis and mitigation in VLIW safety-critical applications. VLSI-SoC 2014: 1-6 - 2013
- [j9]Luca Sterpone:
SEL-UP: A CAD tool for the sensitivity analysis of radiation-induced Single Event Latch-Up. Microelectron. Reliab. 53(9-11): 1311-1314 (2013) - [j8]Luca Sterpone, Mario Porrmann, Jens Hagemeyer:
A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Trans. Computers 62(8): 1508-1525 (2013) - [c58]Khaled Benkrid, Didier Keymeulen, David Merodio, Michael Newell, Rainer Wansch, Umeshkumar D. Patel, Ahmet T. Erdogan, Niels Hadaschik, Luca Sterpone, Jelle Poupaert, Massimo Violante:
Preface. AHS 2013 - [c57]Luca Sterpone, Anees Ullah:
On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs. AHS 2013: 9-14 - [c56]Luca Sterpone, Davide Sabena, Anees Ullah, Mario Porrmann, Jens Hagemeyer, Jørgen Ilstad:
Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. AHS 2013: 184-188 - [c55]Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Luca Sterpone:
On-line testing of permanent radiation effects in reconfigurable systems. DATE 2013: 717-720 - [c54]Matteo Sonza Reorda, Luca Sterpone, Anees Ullah:
An error-detection and self-repairing method for dynamically and partially reconfigurable systems. ETS 2013: 1-7 - [c53]Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone:
Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs. ACM Great Lakes Symposium on VLSI 2013: 7-12 - [c52]Marco Desogus, Matteo Sonza Reorda, Luca Sterpone, V. A. Avantaggiati, G. Audisio, Marco Sabatini:
Validation and robustness assessment of an automotive system. IDT 2013: 1-6 - [c51]Davide Sabena, Matteo Sonza Reorda, Luca Sterpone, Paolo Rech, Luigi Carro:
On the evaluation of soft-errors detection techniques for GPGPUs. IDT 2013: 1-6 - [c50]Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena:
Exploiting the debug interface to support on-line test of control flow errors. IOLTS 2013: 98-103 - [c49]Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
On the development of diagnostic test programs for VLIW processors. VLSI-SoC 2013: 84-89 - [c48]Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
Partition-Based Faults Diagnosis of a VLIW Processor. VLSI-SoC (Selected Papers) 2013: 208-226 - 2012
- [c47]Jens Hagemeyer, Arne Hilgenstein, Dirk Jungewelter, Dario Cozzi, Carmelo Felicetti, Ulrich Rückert, Sebastian Korf, Markus Koester, Fabio Margaglia, Mario Porrmann, Florian Dittmann, Michael Ditze, Julian Harris, Luca Sterpone, Jørgen Ilstad:
A scalable platform for run-time reconfigurable satellite payload processing. AHS 2012: 9-16 - [c46]Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
A new SBST algorithm for testing the register file of VLIW processors. DATE 2012: 412-417 - [c45]Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
On the development of Software-Based Self-Test methods for VLIW processors. DFT 2012: 25-30 - [c44]Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone:
Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs. DFT 2012: 115-120 - [c43]Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, M. Bagatin, Alessandro Paccagnella:
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. DFT 2012: 121-125 - [c42]Luca Sterpone, Davide Sabena, Matteo Sonza Reorda:
A New Fault Injection Approach for Testing Network-on-Chips. PDP 2012: 530-535 - [c41]Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
On the optimized generation of Software-Based Self-Test programs for VLIW processors. VLSI-SoC 2012: 129-134 - [c40]Davide Sabena, Luca Sterpone, Matteo Sonza Reorda:
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors. VLSI-SoC (Selected Papers) 2012: 162-180 - 2011
- [b2]Niccolò Battezzati, Luca Sterpone, Massimo Violante:
Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications. Springer 2011, ISBN 978-1-4419-7594-2, pp. I-VII, 1-220 - [j7]Hipólito Guzmán-Miranda, Luca Sterpone, Massimo Violante, Miguel A. Aguirre, Manuel Gutiérrez-Rizo:
Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs. IEEE Trans. Ind. Electron. 58(3): 814-821 (2011) - [c39]Luca Sterpone, Fabio Margaglia, Markus Köster, Jens Hagemeyer, Mario Porrmann:
Analysis of SEU effects in partially reconfigurable SoPCs. AHS 2011: 129-136 - [c38]Luca Sterpone, Luigi Carro, Debora Matos, Stephan Wong, F. Fakhar:
A new reconfigurable clock-gating technique for low power SRAM-based FPGAs. DATE 2011: 752-757 - [c37]Luca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda:
Fault injection analysis of transient faults in clustered VLIW processors. DDECS 2011: 207-212 - [c36]Jorge Luis Lagos-Benites, Michelangelo Grosso, Luca Sterpone, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini:
A Low-Cost Emulation System for Fast Co-verification and Debug. ETS 2011: 212 - 2010
- [j6]Luca Sterpone:
A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs. ACM Trans. Reconfigurable Technol. Syst. 4(1): 7:1-7:21 (2010) - [c35]Luca Sterpone, Niccolò Battezzati:
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs. DATE 2010: 1231-1236 - [c34]