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Jan Schat
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2010 – 2019
- 2019
- [c11]Jan Schat, Ulrich Möhlmann:
Concurrent Estimation of a PLL Transfer Function by Cross-Correlation with pseudo-random Jitter. ETS 2019: 1-2 - 2018
- [c10]Jan Schat:
On-line RF built-in self-test using noise injection and transmitter signal modulation by phase shifter. DATE 2018: 1003-1004 - [c9]Jan Schat:
ADC test methods using an impure stimulus: A survey. ETS 2018: 1-5 - 2017
- [c8]Jan Schat:
Soft-error detection in Register Files using circular scan. DTIS 2017: 1-3 - [c7]Jan Schat:
ISO26262-compliant soft-error mitigation in register banks. ETS 2017: 1-2
2000 – 2009
- 2009
- [j1]Vladimir A. Zivkovic, Jan Schat, Frank van der Heyden, Geert Seuren:
Core-Based Testing of Embedded Mixed-Signal Modules in a SoC. IEEE Des. Test Comput. 26(3): 78-86 (2009) - [c6]Jan Schat:
On the relationship between stuck-at fault coverage and transition fault coverage. DATE 2009: 1218-1221 - 2008
- [c5]Jan Schat:
Fault Clustering in deep-submicron CMOS Processes. DATE 2008: 511-514 - [c4]Jan Schat:
Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns. DDECS 2008: 235-240 - [c3]Jan Schat:
Evaluation of the Iddq Signature in devices with Gauss-distributed background current. DDECS 2008: 241-246 - 2007
- [c2]Jan Schat:
Testing low-resolution DACs using the Generalized Morse Sequence as Stimulus Sequence for Cancelling DC drift. ICECS 2007: 371-374 - 2006
- [c1]Jan Schat:
Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface. ICECS 2006: 878-881
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