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2020 – today
- 2023
[j25]Constantino Gómez, Filippo Mantovani, Erich Focht, Marc Casas:
HPCG on long-vector architectures: Evaluation and optimization on NEC SX-Aurora and RISC-V. Future Gener. Comput. Syst. 143: 152-162 (2023)- [c72]Alexandre de Limas Santana
, Adrià Armejach, Marc Casas:
Efficient Direct Convolution Using Long SIMD Instructions. PPoPP 2023: 342-353 - [i8]Valentin Le Fèvre, Marc Casas:
Optimization of SpGEMM with Risc-V vector instructions. CoRR abs/2303.02471 (2023) - [i7]Alexandre Valentin Jamet, Lluc Alvarez, Marc Casas:
Characterizing the impact of last-level cache replacement policies on big-data workloads. CoRR abs/2305.06696 (2023) - 2022
- [j24]John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas:
A BF16 FMA is All You Need for DNN Training. IEEE Trans. Emerg. Top. Comput. 10(3): 1302-1314 (2022) - [j23]Juan M. Cebrian, Thibaud Balem, Adrián Barredo, Marc Casas, Miquel Moretó, Alberto Ros, Alexandra Jimborean:
Compiler-Assisted Compaction/Restoration of SIMD Instructions. IEEE Trans. Parallel Distributed Syst. 33(4): 779-791 (2022) - [c71]John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas:
A BF16 FMA is All You Need for DNN Training. ARITH 2022: 9 - [c70]Valentin Le Fèvre, Tetsuzo Usui, Marc Casas:
A Selective Nesting Approach for the Sparse Multi-threaded Cholesky Factorization. ESPM2@SC 2022: 1-9 - [c69]Louis Ledoux, Marc Casas:
A Generator of Numerically-Tailored and High-Throughput Accelerators for Batched GEMMs. FCCM 2022: 1-10 - [c68]Sergi Laut, Marc Casas, Ricard Borrell:
Communication-aware Sparse Patterns for the Factorized Approximate Inverse Preconditioner. HPDC 2022: 148-158 - [c67]Robin Kumar Sharma, Marc Casas:
Task-based Acceleration of Bidirectional Recurrent Neural Networks on Multi-core Architectures. IPDPS 2022: 941-951 - [c66]John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas:
FASE: A Fast, Accurate and Seamless Emulator for Custom Numerical Formats. ISPASS 2022: 144-146 - [c65]Georgios Vavouliotis, Gino Chacon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jiménez, Marc Casas:
Page Size Aware Cache Prefetching. MICRO 2022: 956-974 - [c64]John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas:
FASE: A Fast, Accurate and Seamless Emulator for Custom Numerical Formats. ECML/PKDD (5) 2022: 480-497 - [c63]Paul Caheny, Lluc Alvarez, Marc Casas, Miquel Moretó:
TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models. SC 2022: 80:1-80:15 - [i6]Valentin Le Fèvre, Tetsuzo Usui, Marc Casas:
Optimization of the Sparse Multi-Threaded Cholesky Factorization for A64FX. CoRR abs/2202.09288 (2022) - 2021
- [j22]Cristobal Ortega, Lluc Alvarez, Marc Casas, Ramon Bertran, Alper Buyuktosunoglu, Alexandre E. Eichenberger, Pradip Bose, Miquel Moretó:
Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption. IEEE Trans. Computers 70(1): 1-16 (2021) - [c62]Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero:
PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy. Euro-Par 2021: 599-615 - [c61]Sergi Laut, Ricard Borrell, Marc Casas:
Cache-aware Sparse Patterns for the Factorized Sparse Approximate Inverse Preconditioner. HPDC 2021: 81-93 - [c60]John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas:
Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training. ICMLA 2021: 980-987 - [c59]Georgios Vavouliotis, Lluc Alvarez, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Daniel A. Jiménez, Marc Casas:
Exploiting Page Table Locality for Agile TLB Prefetching. ISCA 2021: 85-98 - [c58]Georgios Vavouliotis, Lluc Alvarez, Boris Grot, Daniel A. Jiménez, Marc Casas:
Morrigan: A Composite Instruction TLB Prefetcher. MICRO 2021: 1138-1153 - [c57]Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau:
Multilevel simulation-based co-design of next generation HPC microprocessors. PMBS 2021: 18-29 - [c56]Constantino Gómez, Filippo Mantovani, Erich Focht, Marc Casas:
Efficiently running SpMV on long vector architectures. PPoPP 2021: 292-303 - 2020
- [j21]Juan M. Cebrian, Adrián Barredo, Helena Caminal, Miquel Moretó, Marc Casas, Mateo Valero:
Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86. Future Gener. Comput. Syst. 112: 832-847 (2020) - [j20]Adrián Barredo, Juan M. Cebrian, Mateo Valero, Marc Casas, Miquel Moretó:
Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies. J. Supercomput. 76(3): 1960-1979 (2020) - [j19]Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó:
Using Arm's scalable vector extension on stencil codes. J. Supercomput. 76(3): 2039-2062 (2020) - [j18]Maria Barreda, José Ignacio Aliaga, Vicenç Beltran, Marc Casas:
Iteration-fusing conjugate gradient for sparse linear systems with MPI + OmpSs. J. Supercomput. 76(9): 6669-6689 (2020) - [c55]Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero:
Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions. HPCA 2020: 717-728 - [c54]John Osorio Ríos, Adrià Armejach, Gulrukh Khattak, Eric Petit, Sofia Vallecorsa, Marc Casas:
Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors. ICMLA 2020: 49-56 - [c53]Robin Kumar Sharma, Marc Casas:
Wavefront parallelization of recurrent neural networks on multi-core architectures. ICS 2020: 5:1-5:12 - [c52]Vladimir Dimic, Miquel Moretó, Marc Casas, Jan Ciesko, Mateo Valero:
RICH: implementing reductions in the cache hierarchy. ICS 2020: 16:1-16:13 - [c51]Isaac Sánchez Barrera, David Black-Schaffer, Marc Casas, Miquel Moretó, Anastasiia Stupnikova, Mihail Popov:
Modeling and optimizing NUMA effects and prefetching with machine learning. ICS 2020: 34:1-34:13 - [c50]Alexandre Valentin Jamet, Lluc Alvarez, Daniel A. Jiménez, Marc Casas:
Characterizing the impact of last-level cache replacement policies on big-data workloads. IISWC 2020: 134-144 - [c49]Isaac Boixaderas, Darko Zivanovic, Sergi Moré, Javier Bartolome, David Vicente, Marc Casas, Paul M. Carpenter, Petar Radojkovic, Eduard Ayguadé:
Cost-aware prediction of uncorrected DRAM errors in the field. SC 2020: 61 - [c48]Luc Jaulmes, Miquel Moretó, Mateo Valero, Mattan Erez, Marc Casas:
Runtime-guided ECC protection using online estimation of memory vulnerability. SC 2020: 76 - [i5]Sicong Zhuang, A. Cristiano I. Malossi, Marc Casas:
Reducing Data Motion to Accelerate the Training of Deep Neural Networks. CoRR abs/2004.02297 (2020) - [i4]Marc Ortiz, Florian Scheidegger, Marc Casas, A. Cristiano I. Malossi, Eduard Ayguadé:
Generating Efficient DNN-Ensembles with Evolutionary Computation. CoRR abs/2009.08698 (2020)
2010 – 2019
- 2019
- [j17]Marc Casas, Wilfried N. Gansterer, Elias Wimmer:
Resilient gossip-inspired all-reduce algorithms for high-performance computing: Potential, limitations, and open questions. Int. J. High Perform. Comput. Appl. 33(2) (2019) - [j16]Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Mateo Valero:
On the maturity of parallel applications for asymmetric multi-core processors. J. Parallel Distributed Comput. 127: 105-115 (2019) - [j15]Pavan Balaji, Marc Casas:
Special issue on the message passing interface. Parallel Comput. 86: 14-15 (2019) - [j14]Thomas Grass, Trevor E. Carlson, Alejandro Rico, Germán Ceballos, Eduard Ayguadé, Marc Casas, Miquel Moretó:
Sampled Simulation of Task-Based Programs. IEEE Trans. Computers 68(2): 255-269 (2019) - [j13]Adrià Armejach, Marc Casas, Miquel Moretó:
Design trade-offs for emerging HPC processors based on mobile market technology. J. Supercomput. 75(9): 5717-5740 (2019) - [c47]Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero:
POSTER: An Optimized Predication Execution for SIMD Extensions. PACT 2019: 479-480 - [c46]Ferran Plana Rius, Cecilio Angulo Bahón, Marc Casas, Josep Maria Mirats Tur:
Convolutional Neural Network Training with Dynamic Epoch Ordering. CCIA 2019: 105-114 - [c45]Dimitrios Chasapis, Miquel Moretó, Martin Schulz, Barry Rountree, Mateo Valero, Marc Casas:
Power efficient job scheduling by predicting the impact of processor manufacturing variability. ICS 2019: 296-307 - [c44]Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele:
Optimizing computation-communication overlap in asynchronous task-based programs. ICS 2019: 380-391 - [c43]Daniel Ruiz, Filippo Spiga, Marc Casas, Marta Garcia-Gasulla, Filippo Mantovani:
Open-Source Shared Memory implementation of the HPCG benchmark: analysis, improvements and evaluation on Cavium ThunderX2. HPCS 2019: 225-232 - [c42]Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas:
A Vulnerability Factor for ECC-protected Memory. IOLTS 2019: 176-181 - [c41]Constantino Gómez, Francesc Martínez, Adrià Armejach, Miquel Moretó, Filippo Mantovani, Marc Casas:
Design Space Exploration of Next-Generation HPC Machines. IPDPS 2019: 54-65 - [c40]Alejandro Rico, Isaac Sánchez Barrera, José A. Joao, Joshua Randall, Marc Casas, Miquel Moretó:
On the Benefits of Tasking with OpenMP. IWOMP 2019: 217-230 - [c39]Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele:
Optimizing computation-communication overlap in asynchronous task-based programs: poster. PPoPP 2019: 415-416 - 2018
- [j12]Helena Caminal, Diego Caballero, Juan M. Cebrian, Roger Ferrer, Marc Casas, Miquel Moretó, Xavier Martorell, Mateo Valero:
Performance and energy effects on task-based parallelized applications - User-directed versus manual vectorization. J. Supercomput. 74(6): 2627-2637 (2018) - [j11]Paul Caheny, Lluc Alvarez, Said Derradji, Mateo Valero, Miquel Moretó, Marc Casas:
Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach. IEEE Trans. Parallel Distributed Syst. 29(5): 1174-1187 (2018) - [j10]Luc Jaulmes, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas:
Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers. IEEE Trans. Parallel Distributed Syst. 29(9): 1961-1974 (2018) - [c38]Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó:
Stencil codes on a vector length agnostic architecture. PACT 2018: 13:1-13:12 - [c37]Emilio Castillo, Lluc Alvarez, Miquel Moretó, Marc Casas, Enrique Vallejo, José Luis Bosque, Ramón Beivide, Mateo Valero:
Architectural Support for Task Dependence Management with Flexible Software Scheduling. HPCA 2018: 283-295 - [c36]Isaac Sánchez Barrera, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas:
Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies. ICS 2018: 207-217 - [c35]Lluc Alvarez, Marc Casas, Jesús Labarta, Eduard Ayguadé, Mateo Valero, Miquel Moretó:
Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs. ICS 2018: 218-228 - [c34]Cristobal Ortega, Victor Garcia, Miquel Moretó, Marc Casas, Roxana Rusitoru:
Data Prefetching on In-order Processors. HPCS 2018: 322-329 - [c33]Isaac Sánchez Barrera, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Graph partitioning applied to DAG scheduling to reduce NUMA effects. PPoPP 2018: 419-420 - [c32]Paul Caheny, Lluc Alvarez, Mateo Valero, Miquel Moretó, Marc Casas:
Runtime-assisted cache coherence deactivation in task parallel programs. SC 2018: 35:1-35:12 - [c31]Valentin Le Fèvre, Leonardo Bautista-Gomez, Osman S. Unsal, Marc Casas:
Approximating a Multi-Grid Solver. PMBS@SC 2018: 97-107 - [c30]Kallia Chronaki, Marc Casas, Miquel Moretó, Jaume Bosch, Rosa M. Badia:
TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism. ISC 2018: 389-409 - [i3]Marc Ortiz, Adrián Cristal, Eduard Ayguadé, Marc Casas:
Low-Precision Floating-Point Schemes for Neural Network Training. CoRR abs/1804.05267 (2018) - [i2]Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas:
Memory Vulnerability: A Case for Delaying Error Reporting. CoRR abs/1810.06472 (2018) - 2017
- [j9]Marc Casas, Greg Bronevetsky:
Prediction of the impact of network switch utilization on application performance via active measurement. Parallel Comput. 67: 38-56 (2017) - [j8]Kallia Chronaki, Alejandro Rico, Marc Casas, Miquel Moretó, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Task Scheduling Techniques for Asymmetric Multi-Core Systems. IEEE Trans. Parallel Distributed Syst. 28(7): 2074-2087 (2017) - [c29]Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero:
Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals. Euro-Par 2017: 247-259 - [c28]Ilia Pietri, Sicong Zhuang, Marc Casas, Miquel Moretó, Rizos Sakellariou:
Evaluating Scientific Workflow Execution on an Asymmetric Multicore Processor. Euro-Par Workshops 2017: 439-451 - [c27]Sicong Zhuang, Marc Casas:
Iteration-fusing conjugate gradient. ICS 2017: 21:1-21:10 - [c26]Cristobal Ortega, Miquel Moretó, Marc Casas, Ramon Bertran, Alper Buyuktosunoglu, Alexandre E. Eichenberger, Pradip Bose:
libPRISM: an intelligent adaptation of prefetch and SMT levels. ICS 2017: 28:1-28:10 - [c25]Iulian Brumar, Marc Casas, Miquel Moretó, Mateo Valero, Gurindar S. Sohi:
ATM: Approximate Task Memoization in the Runtime System. IPDPS 2017: 1140-1150 - [c24]Damian Roca, Daniel Nemirovsky, Marc Casas, Miquel Moretó, Mateo Valero, Mario Nemirovsky:
iQ: An Efficient and Flexible Queue-Based Simulation Framework. MASCOTS 2017: 143-149 - 2016
- [j7]Dimitrios Chasapis, Marc Casas, Miquel Moretó, Raul Vidal, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite. ACM Trans. Archit. Code Optim. 12(4): 41:1-41:22 (2016) - [j6]Marc Casas, Greg Bronevetsky:
Evaluation of HPC Applications' Memory Resource Consumption via Active Measurement. IEEE Trans. Parallel Distributed Syst. 27(9): 2560-2573 (2016) - [c23]Paul Caheny, Marc Casas, Miquel Moretó, Hervé Gloaguen, Maxime Saintes, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling. PACT 2016: 275-286 - [c22]Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware. PACT 2016: 415-417 - [c21]Dimitrios Chasapis, Marc Casas, Miquel Moretó, Martin Schulz, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes. ICS 2016: 5:1-5:12 - [c20]Emilio Castillo, Miquel Moretó, Marc Casas, Lluc Alvarez, Enrique Vallejo, Kallia Chronaki, Rosa M. Badia, José Luis Bosque, Ramón Beivide, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
CATA: Criticality Aware Task Acceleration for Multicore Processors. IPDPS 2016: 413-422 - [c19]Thomas Grass, Alejandro Rico, Marc Casas, Miquel Moretó, Eduard Ayguadé:
TaskPoint: Sampled simulation of task-based programs. ISPASS 2016: 296-306 - [c18]Thomas Grass, César Allande, Adrià Armejach, Alejandro Rico, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas, Miquel Moretó:
MUSA: a multi-level simulation approach for next-generation HPC machines. SC 2016: 526-537 - 2015
- [j5]Sui Chen, Greg Bronevetsky, Bin Li, Marc Casas-Guix, Lu Peng:
A framework for evaluating comprehensive fault resilience mechanisms in numerical programs. J. Supercomput. 71(8): 2963-2984 (2015) - [c17]Lluc Alvarez, Miquel Moretó, Marc Casas, Emilio Castillo, Xavier Martorell, Jesús Labarta, Eduard Ayguadé, Mateo Valero:
Runtime-Guided Management of Scratchpad Memories in Multicore Architectures. PACT 2015: 379-391 - [c16]Marc Casas, Miquel Moretó, Lluc Alvarez, Emilio Castillo, Dimitrios Chasapis, Timothy Hayes, Luc Jaulmes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Runtime-Aware Architectures. Euro-Par 2015: 16-27 - [c15]Lluc Alvarez, Lluís Vilanova, Miquel Moretó, Marc Casas, Marc González, Xavier Martorell, Nacho Navarro, Eduard Ayguadé, Mateo Valero:
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures. ISCA 2015: 720-732 - [c14]Raul Vidal, Marc Casas, Miquel Moretó, Dimitrios Chasapis, Roger Ferrer, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads. IWOMP 2015: 60-72 - [c13]Luc Jaulmes, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero:
Exploiting asynchrony from exact forward recovery for DUE in iterative solvers. SC 2015: 53:1-53:12 - [i1]David Prat, Cristobal Ortega, Marc Casas, Miquel Moretó, Mateo Valero:
Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7. CoRR abs/1501.02282 (2015) - 2014
- [j4]Mateo Valero, Miquel Moretó, Marc Casas, Eduard Ayguadé, Jesús Labarta:
Runtime-Aware Architectures: A First Approach. Supercomput. Front. Innov. 1(1): 29-44 (2014) - [c12]Thomas Grass, Alejandro Rico, Marc Casas, Miquel Moretó, Alex Ramírez:
Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors. Euro-Par Workshops (2) 2014: 218-229 - [c11]Marc Casas, Greg Bronevetsky:
Active Measurement of the Impact of Network Switch Utilization on Application Performance. IPDPS 2014: 165-174 - [c10]Marc Casas, Greg Bronevetsky:
Active Measurement of Memory Resource Consumption. IPDPS 2014: 995-1004 - 2013
- [c9]Martin Schulz, James F. Belak, Abhinav Bhatele, Peer-Timo Bremer, Greg Bronevetsky, Marc Casas, Todd Gamblin, Katherine E. Isaacs, Ignacio Laguna, Joshua A. Levine, Valerio Pascucci, David F. Richards, Barry Rountree:
Performance Analysis Techniques for the Exascale Co-Design Process. PARCO 2013: 19-32 - 2012
- [c8]Marc Casas-Guix, Bronis R. de Supinski, Greg Bronevetsky, Martin Schulz:
Fault resilience of the algebraic multi-grid solver. ICS 2012: 91-100 - [c7]Steena D. S. Monteiro, Greg Bronevetsky, Marc Casas-Guix:
Abstract: Autonomic Modeling of Data-Driven Application Behavior. SC Companion 2012: 1485-1486 - [c6]Steena D. S. Monteiro, Greg Bronevetsky, Marc Casas-Guix:
Poster: Autonomic Modeling of Data-Driven Application Behavior. SC Companion 2012: 1487 - 2011
- [j3]Marc Casas, Harald Servat, Rosa M. Badia, Jesús Labarta:
Extracting the optimal sampling frequency of applications using spectral analysis. Concurr. Comput. Pract. Exp. 24(3): 237-259 (2011) - [j2]Juan Gonzalez, Judit Giménez, Marc Casas, Miquel Moretó, Alex Ramírez, Jesús Labarta, Mateo Valero:
Simulating Whole Supercomputer Applications. IEEE Micro 31(3): 32-45 (2011) - [c5]Germán Llort, Marc Casas, Harald Servat, Kevin A. Huck, Judit Giménez, Jesús Labarta:
Trace Spectral Analysis toward Dynamic Levels of Detail. ICPADS 2011: 332-339 - 2010
- [b1]Marc Casas:
Spectral analysis of executions of computer programs and its applications on performance analysis. Polytechnic University of Catalonia, Spain, 2010 - [j1]Marc Casas, Rosa M. Badia, Jesús Labarta:
Automatic Phase Detection and Structure Extraction of MPI Applications. Int. J. High Perform. Comput. Appl. 24(3): 335-360 (2010)
2000 – 2009
- 2008
- [c4]Marc Casas, Rosa M. Badia, Jesús Labarta:
Prediction of behavior of MPI applications. CLUSTER 2008: 242-251 - [c3]Marc Casas, Rosa M. Badia, Jesús Labarta:
Automatic analysis of speedup of MPI applications. ICS 2008: 349-358 - 2007
- [c2]Marc Casas, Rosa M. Badia, Jesús Labarta:
Automatic Structure Extraction from MPI Applications Tracefiles. Euro-Par 2007: 3-12 - [c1]Marc Casas, Rosa M. Badia, Jesús Labarta:
Automatic Phase Detection of MPI Applications. PARCO 2007: 129-136
Coauthor Index
[j23] [c63] [j22] [c62] [j21] [j20] [j19] [c55] [c52] [c51] [c48] [j16] [j14] [j13] [c47] [c45] [c44] [c42] [c41] [c40] [c39] [j12] [j11] [j10] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c30] [i2] [j8] [c29] [c28] [c26] [c25] [c24] [j7] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [i1] [j4] [c12] [j2]