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ORCIDMohammad Taherzadeh-Sani
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2020 – today
- 2023
[j19]Maryam Ghamati, Mohammad Taherzadeh-Sani
, Frederic Nabki:
A Compact Wideband Two-Stage LNA with Multiple Notches for Out-of-Band Filtering Using Center-Tap Inductors. Circuits Syst. Signal Process. 42(5): 2573-2588 (2023)- [j18]Amin Pourvali Kakhki, Mohammad Taherzadeh-Sani, Frederic Nabki:
An Energy Efficient Coherent IR-UWB Receiver With Non-Coherent-Assisted Synchronization. IEEE Trans. Circuits Syst. I Regul. Pap. 70(8): 3154-3166 (2023) - [j17]Maryam Ghamati, Mohammad Taherzadeh-Sani, Frederic Nabki, Milica Popovic:
Integrated Fast UWB Time-Domain Microwave Breast Screening. IEEE Trans. Instrum. Meas. 72: 1-12 (2023) - 2021
- [j16]Bahaa Radi, Mohammadreza Sanadgol Nezami, Mohammad Taherzadeh-Sani, Frederic Nabki, Michaël Ménard, Odile Liboiron-Ladouceur:
A 22-Gb/s Time-Interleaved Low-Power Optical Receiver With a Two-Bit Integrating Front End. IEEE J. Solid State Circuits 56(1): 310-323 (2021) - 2020
- [j15]Ehsan Rahiminejad, Mehdi Saberi, Reza Lotfi, Mohammad Taherzadeh-Sani, Frederic Nabki:
A Low-Voltage High-Precision Time-Domain Winner-Take-All Circuit. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 4-8 (2020) - [j14]Mohammad Taherzadeh-Sani, Bahaa Radi, Mohammadreza Sanadgol Nezami, Michaël Ménard, Odile Liboiron-Ladouceur, Frederic Nabki:
A 17 Gbps 156 fJ/bit Two-Channel Optical Receiver With Optical-Input Split and Delay in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(7): 2288-2296 (2020) - [c24]Amin Aghighi, Armin Tajalli, Mohammad Taherzadeh-Sani:
A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors. VLSI-SOC 2020: 171-175
2010 – 2019
- 2019
- [j13]Amir Bazrafshan, Mohammad Taherzadeh-Sani, Frederic Nabki:
An Analog LO Harmonic Suppression Technique for SDR Receivers. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 182-192 (2019) - [i1]Mohsen Annabestani, Mahshid Nasserian, Fatemeh Hasanzadeh, Mohammad Taherzadeh-Sani, Alireza Hassanzadeh:
An Algebraic Approach to Fast Estimation of the Threshold Voltage of Junctionless Double Gate MOSFETs Using the Gram Schmidt Method. CoRR abs/1905.06802 (2019) - 2018
- [j12]Mohammad Javad Zavarei, Mohammad Taherzadeh-Sani:
Envelope-tracking common-drain CMOS power amplifier with a switching-only supply modulator for LTE applications. Microelectron. J. 72: 24-31 (2018) - [j11]Amir Bazrafshan, Mohammad Taherzadeh-Sani, Frederic Nabki:
A 0.8-4-GHz Software-Defined Radio Receiver With Improved Harmonic Rejection Through Non-Overlapped Clocking. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3186-3195 (2018) - 2017
- [j10]Mohammad Taherzadeh-Sani, Michiel Soer, Dominic Deslandes, Frederic Nabki:
65 nm CMOS switching discontinuous-conduction mode buck converter with 330 ns start-up time for light-load power-cycled applications. IET Circuits Devices Syst. 11(3): 267-273 (2017) - [j9]Mohammad Taherzadeh-Sani, Said M. Hussain Hussaini, Hamidreza Rezaee-Dehsorkh, Frederic Nabki, Mohamad Sawan:
A 170-dB Ω CMOS TIA With 52-pA Input-Referred Noise and 1-MHz Bandwidth for Very Low Current Sensing. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1756-1766 (2017) - [c23]Quentin Sauve, Damien Favre, Gabriel Morin-Laporte, Mohammad Taherzadeh-Sani, Nicolas Constantin, Frederic Nabki:
A calibration-free 13-bit 0.9 V differential SAR-ADC with hybrid DAC and dithering. ISCAS 2017: 1-4 - 2016
- [c22]Saeed Mehrjoo, Mohammad Taherzadeh-Sani, Frederic Nabki:
A 27 mV output ripple 92% efficiency buck converter using a multi-bit delta-sigma modulator controller and segmented output switch in 180 nm CMOS. ICECS 2016: 129-132 - [c21]Amin Aghighi, Abdul Hafiz Alameh, Mohammad Taherzadeh-Sani, Frederic Nabki:
A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors. ICECS 2016: 217-220 - [c20]Ali Badiey, Reza Papi, Navid Rahmanikia, Mohammad Taherzadeh-Sani, Frederic Nabki:
Single-ended impedance-modulation equalization for low-power differential voltage-mode drivers. ICECS 2016: 644-647 - 2015
- [j8]Mohammad Taherzadeh-Sani, Frederic Nabki:
A 350-MS/s Continuous-Time Delta-Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1914-1919 (2015) - [c19]Monireh Eslami, Mohammad Taherzadeh-Sani, Frederic Nabki:
A 1-V 690 μW 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13μm CMOS. ISCAS 2015: 289-292 - [c18]Parvaneh Saffari, Mohammad Taherzadeh-Sani, Ali Basaligheh, Frederic Nabki, Mohamad Sawan:
Low-energy CMOS common-drain power amplifier for short-range applications. NEWCAS 2015: 1-4 - 2014
- [j7]Mohammad Taherzadeh-Sani, Reza Lotfi, Frederic Nabki:
A 10-bit 110 kS/s 1.16 µW SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 584-588 (2014) - 2013
- [j6]Mohammad Taherzadeh-Sani, Anas A. Hamoui:
A Reconfigurable and Power-Scalable 10-12 Bit 0.4-44 MS/s Pipelined ADC With 0.35-0.5 pJ/Step in 1.2 V 90 nm Digital CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 74-83 (2013) - 2012
- [j5]Mohammad Taherzadeh-Sani, Anas A. Hamoui:
Correction to "A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS" [Mar 11 660-668]. IEEE J. Solid State Circuits 47(6): 1497 (2012) - 2011
- [j4]Mohammad Taherzadeh-Sani, Anas A. Hamoui:
A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS. IEEE J. Solid State Circuits 46(3): 660-668 (2011) - 2010
- [j3]Mohammad Taherzadeh-Sani, Anas A. Hamoui:
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 652-657 (2010) - [c17]Mohammad Taherzadeh-Sani, Anas A. Hamoui:
A reconfigurable 10-12b 0.4-44MS/s pipelined ADC with 0.35-0.5pJ/step in 1.2V 90nm digital CMOS. ESSCIRC 2010: 382-385
2000 – 2009
- 2007
- [c16]Mohammad Taherzadeh-Sani, Anas A. Hamoui:
Power Optimization of Pipelined ADCs with High-Order Digital Gain Calibration. ICECS 2007: 661-664 - 2006
- [j2]Mohammad Taherzadeh-Sani, Anas A. Hamoui:
Digital Background Calibration of Capacitor-Mismatch Errors in Pipelined ADCs. IEEE Trans. Circuits Syst. II Express Briefs 53-II(9): 966-970 (2006) - [c15]Mohammad Taherzadeh-Sani, Anas A. Hamoui:
Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs. ISCAS 2006 - [c14]Mohammad Taherzadeh-Sani, Anas A. Hamoui:
Analysis of dynamic element matching (DEM) in pipelined ADCs. ISCAS 2006 - [c13]Anas A. Hamoui, T. Alhajj, Mohammad Taherzadeh-Sani:
Behavioral modeling of Opamp gain and dynamic effectsfor power optimization of Delta-Sigma modulators and pipelined ADCs. ISLPED 2006: 330-333 - 2005
- [c12]Reza Lotfi, Mohammad Taherzadeh-Sani, Omid Shoaei:
Power consumption issues in high-speed high-resolution pipelined A/D converters. ISCAS (5) 2005: 4618-4621 - [c11]Mohammad Taherzadeh-Sani, Ali Abbasian, Behnam Amelifard, Ali Afzali-Kusha:
Modeling of MOS transistors based on genetic algorithm and simulated annealing. ISCAS (6) 2005: 6218-6221 - 2004
- [c10]Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei:
Systematic Design for Optimization of High-Resolution Pipelined ADCs. DATE 2004: 678-679 - [c9]Reza Lotfi, Mohammad Taherzadeh-Sani, Omid Shoaei:
A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-µm CMOS [convereter read converter]. ISCAS (1) 2004: 69-72 - [c8]Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei:
A pseudo-class-AB telescopic-cascode operational amplifier. ISCAS (1) 2004: 737-740 - 2003
- [j1]Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei:
Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications. Integr. 36(4): 175-189 (2003) - [c7]Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei:
An analytical approach to the estimation of dynamic non-linearity parameters in pipeline A/D converters. ESSCIRC 2003: 715-718 - [c6]Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei:
A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs. ICCAD 2003: 367-370 - [c5]Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei:
Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters. ICCAD 2003: 371-374 - [c4]Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei:
A novel frequency compensation technique for two-stage CMOS operational amplifiers. ICECS 2003: 256-259 - [c3]Reza Lotfi, Mohammad Taherzadeh-Sani, Omid Shoaei:
A 1.5-V 12-bit 75M-samples/s fully-differential low-power sample-and-hold amplifier in 0.25-μm CMOS. ICECS 2003: 814-817 - [c2]Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei:
An analytical approach to the estimation of the spurious-free dynamic range in pipeline A/D converters. ICECS 2003: 946-949 - [c1]Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei:
A low-power design methodology for high-resolution pipelined analog-to-digital converters. ISLPED 2003: 334-339
Coauthor Index
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