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Lin Ma 0007
Person information
- affiliation: Washington University in St. Louis, St.Louis, MO, USA
- affiliation: Huawei America Research Center, Santa Clara, CA, USA
Other persons with the same name
- Lin Ma — disambiguation page
- Lin Ma 0001
— Harbin Institute of Technology, Department of Electronics and Information Engineering, Communication Research Center, China
- Lin Ma 0002
— Meituan Inc., Beijing, China (and 3 more)
- Lin Ma 0003
— Harbin Institute of Technology, School of Computer Science and Technology, China
- Lin Ma 0004
— Zhejiang University, Hangzhou, China
- Lin Ma 0005
— Lille University of Science and Technology, France
- Lin Ma 0006 — Carnegie Mellon University, PA, USA
- Lin Ma 0008 — Shanghai Jiao Tong University, State Key Laboratory of Advanced Optical Communication Systems and Networks, China
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2010 – 2019
- 2019
- [c9]Wei Han, Daniel Mawhirter, Bo Wu, Lin Ma, Chen Tian:
FLARE: Flexibly Sharing Commodity GPUs to Enforce QoS and Improve Utilization. LCPC 2019: 32-48 - 2018
- [j2]Lin Ma, Roger D. Chamberlain, Kunal Agrawal, Chen Tian, Ziang Hu:
Analysis of classic algorithms on highly-threaded many-core architectures. Future Gener. Comput. Syst. 82: 528-543 (2018) - [c8]Wei Ling, Chen Tian, Lin Ma, Ziang Hu:
Lite-Service: A Framework to Build and Schedule Telecom Applications in Device, Edge and Cloud. HPCC/SmartCity/DSS 2018: 708-717 - 2015
- [c7]Jiachen Xue, Chong Chen, Lin Ma, Teng Su, Chen Tian, Wenqin Zheng, Ziang Hu:
Task-D: A Task Based Programming Framework for Distributed System. HPCC/CSS/ICESS 2015: 1663-1668 - 2014
- [j1]Lin Ma, Kunal Agrawal, Roger D. Chamberlain:
A memory access model for highly-threaded many-core architectures. Future Gener. Comput. Syst. 30: 202-215 (2014) - [c6]Lin Ma, Roger D. Chamberlain, Kunal Agrawal:
Performance modeling for highly-threaded many-core GPUs. ASAP 2014: 84-91 - [c5]Lin Ma, Roger D. Chamberlain, Kunal Agrawal:
Analysis of classic algorithms on GPUs. HPCS 2014: 65-73 - [c4]Lin Ma, Kunal Agrawal, Roger D. Chamberlain:
Theoretical analysis of classic algorithms on highly-threaded many-core GPUs. PPoPP 2014: 391-392 - 2012
- [c3]Lin Ma, Roger D. Chamberlain:
A Performance Model for Memory Bandwidth Constrained Applications on Graphics Engines. ASAP 2012: 24-31 - [c2]Lin Ma, Kunal Agrawal, Roger D. Chamberlain:
A Memory Access Model for Highly-threaded Many-core Architectures. ICPADS 2012: 339-347 - 2011
- [c1]Lin Ma, Roger D. Chamberlain, Jeremy D. Buhler
, Mark A. Franklin:
Bloom Filter Performance on Graphics Engines. ICPP 2011: 522-531
Coauthor Index
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last updated on 2024-08-28 22:31 CEST by the dblp team
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