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2020 – today
- 2023
[j22]Chiun-Li Chin, Chia-Chun Lin, Jing-Wen Wang, Wei-Cheng Chin, Yu-Hsiang Chen, Sheng-Wen Chang, Pei-Chen Huang, Xin Zhu
, Yu-Lun Hsu, Shing-Hong Liu:
A Wearable Assistant Device for the Hearing Impaired to Recognize Emergency Vehicle Sirens with Edge Computing. Sensors 23(17): 7454 (2023)- 2022
- [j21]Xiang-Min Yang, Pei-Pei Chen, Hsiao-Yu Chiang, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 29-34 (2022) - [j20]Chang-Cheng Ko, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
Majority Logic Circuit Minimization Using Node Addition and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 642-655 (2022) - [j19]Chia-Chun Lin, Ciao-Syun Lin, You-Hsuen Tsai, Yung-Chih Chen, Chun-Yao Wang:
Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1412-1422 (2022) - 2021
- [j18]Chia-Cheng Wu, Yi-Hsiang Hu, Chia-Chun Lin, Yung-Chih Chen, Juinn-Dar Huang, Chun-Yao Wang:
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model. ACM J. Emerg. Technol. Comput. Syst. 17(2): 15:1-15:23 (2021) - [c25]Chia-Chun Lin, Hsin-Ping Yen, Sheng-Hsiu Wei, Pei-Pei Chen, Yung-Chih Chen, Chun-Yao Wang:
A General Equivalence Checking Framework for Multivalued Logic. ASP-DAC 2021: 61-66 - [c24]Kit Seng Tam, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
An Efficient Approximate Node Merging with an Error Rate Guarantee. ASP-DAC 2021: 266-271 - [c23]Hsin-Tsung Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays. ISQED 2021: 316 - [c22]Wen-Chih Hsu, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
On Reduction of Computations for Threshold Function Identification. SoCC 2021: 146-151 - [c21]Yi-Ting Lin, Chun-Jui Chen, Pei-Yi Kuo, Si-Huei Lee, Chia-Chun Lin, Yun-Ju Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
An IMU-aided Fitness System. SoCC 2021: 224-229 - [c20]Shiuan-Hau Huang, Hsin-Ping Yen, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
Cluster Tool Performance Analysis using Graph Database. SoCC 2021: 230-235 - 2020
- [j17]Hsiao-Yu Chiang, Yung-Chih Chen, De-Xuan Ji, Xiang-Min Yang, Chia-Chun Lin, Chun-Yao Wang:
LOOPLock: Logic Optimization-Based Cyclic Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2178-2191 (2020) - [j16]Chia-Chun Lin, Chin-Heng Liu, Yung-Chih Chen, Chun-Yao Wang:
A New Necessary Condition for Threshold Function Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5304-5308 (2020) - [c19]Ya-Chun Chang, Chia-Chun Lin, Yi-Ting Lin, Yung-Chih Chen, Chun-Yao Wang:
A Convolutional Result Sharing Approach for Binarized Neural Network Inference. DATE 2020: 780-785 - [c18]Teng-Chia Wang, Yan-Ping Chang, Chun-Jui Chen, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement. ISQED 2020: 173-178 - [c17]Chun-Jui Chen, Yi-Ting Lin, Chia-Chun Lin, Yung-Chih Chen, Yun-Ju Lee, Chun-Yao Wang:
Rehabilitation System for Limbs using IMUs. ISQED 2020: 285-291 - [c16]Chia-Chun Lin, Kit Seng Tam, Chana-Cheng Ko, Hsin-Ping Yen, Shenz-Hsiu Wei, Yung-Chih Chen, Chun-Yao Wang:
A Dynamic Expansion Order Algorithm for the SAT-based Minimization. SoCC 2020: 271-276
2010 – 2019
- 2019
- [j15]Chieh Lee, Xun Xu, Chia-Chun Lin:
Using Online User-Generated Reviews to Predict Offline Box-Office Sales and Online DVD Store Sales in the O2O Era. J. Theor. Appl. Electron. Commer. Res. 14(1) (2019) - [j14]Chin-Heng Liu, Chia-Chun Lin, Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, Shigeru Yamashita:
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2284-2297 (2019) - [c15]De-Xuan Ji, Hsiao-Yu Chiang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang:
A Glitch Key-Gate for Logic Locking. SoCC 2019: 74-79 - [c14]Yan-Ping Chang, Teng-Chia Wang, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises. SoCC 2019: 197-202 - 2018
- [j13]Hsin-Pei Wang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang:
On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2842-2852 (2018) - [c13]Tung-Yuan Lee, Chia-Cheng Wu, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang:
Logic optimization with considering boolean relations. DATE 2018: 761-766 - [c12]Yung-An Lai, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang:
Efficient synthesis of approximate threshold logic circuits with an error rate guarantee. DATE 2018: 773-778 - [c11]Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, Chun-Yao Wang:
Using range-equivalent circuits for facilitating bounded sequential equivalence checking. VLSI-DAT 2018: 1-4 - 2017
- [j12]Yu-Ling Hsueh, He Ma, Chia-Chun Lin, Roger Zimmermann:
An efficient approach to finding potential products continuously. Inf. Syst. 65: 22-35 (2017) - [j11]Yu-Ling Hsueh, Chia-Chun Lin, Chia-Che Chang:
An Efficient Indexing Method for Skyline Computations with Partially Ordered Domains. IEEE Trans. Knowl. Data Eng. 29(5): 963-976 (2017) - [c10]Chia-Chun Lin, Chiao-Wei Huang, Chun-Yao Wang, Yung-Chih Chen:
In&Out: Restructuring for threshold logic network optimization. ISQED 2017: 413-418 - 2016
- [c9]Yu-Ling Hsueh, Wei-Li Lai, Chia-Chun Lin, Pierre Pascal Lindenberg:
Traffic Anomalous Region Detection Model. IIAI-AAI 2016: 647-650 - 2015
- [j10]Chuan Qin, Chin-Chen Chang, Chia-Chun Lin:
An adaptive reversible steganographic scheme based on the just noticeable distortion. Multim. Tools Appl. 74(6): 1983-1995 (2015) - [j9]Chia-Chun Lin, Susmita Sur-Kolay, Niraj K. Jha:
PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1221-1234 (2015) - 2014
- [j8]Chia-Chun Lin, Niraj K. Jha:
RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits. ACM J. Emerg. Technol. Comput. Syst. 10(2): 14:1-14:25 (2014) - [j7]Chia-Chun Lin, Amlan Chakrabarti, Niraj K. Jha:
QLib: Quantum module library. ACM J. Emerg. Technol. Comput. Syst. 11(1): 7:1-7:20 (2014) - [j6]Chia-Chun Lin, Amlan Chakrabarti, Niraj K. Jha:
FTQLS: Fault-Tolerant Quantum Logic Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1350-1363 (2014) - [c8]Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang:
Rewiring for threshold logic circuit minimization. DATE 2014: 1-6 - 2013
- [j5]Chia-Chun Lin, Amlan Chakrabarti, Niraj K. Jha:
Optimized Quantum Gate Library for Various Physical Machine Descriptions. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2055-2068 (2013) - 2012
- [j4]Regina Juchun Chu, Anita Zichun Chu, Cathy Weng, Chin-Chung Tsai, Chia-Chun Lin:
Transformation for adults in an Internet-based learning environment - is it necessary to be self-directed? Br. J. Educ. Technol. 43(2): 205-216 (2012) - [j3]Xing-Tian Wang, Chin-Chen Chang, Chia-Chun Lin, Mingchu Li:
A novel multi-group exploiting modification direction method based on switch map. Signal Process. 92(6): 1525-1535 (2012) - [c7]Chin-Chen Chang, Ngoc-Tu Huynh, Chia-Chun Lin:
Strong Tamper-Localization, Visual Secret Sharing Scheme Based on Exploiting Modification Direction. AsiaJCIS 2012: 10-16 - [c6]Amlan Chakrabarti, Chia-Chun Lin, Niraj K. Jha:
Design of Quantum Circuits for Random Walk Algorithms. ISVLSI 2012: 135-140 - 2011
- [c5]Shaikh Anowarul Fattah, Chia-Chun Lin, Sun-Yuan Kung:
A mutual information based approach for evaluating the quality of clustering. ICASSP 2011: 601-604
2000 – 2009
- 2008
- [j2]Yu-Kun Lin, Chia-Chun Lin, Tzu-Yun Kuo, Tian-Sheuan Chang:
A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1526-1535 (2008) - [c4]Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang:
A 242mW, 10mm21080p H.264/AVC high profile encoder chip. DAC 2008: 78-83 - [c3]Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang:
A 242mW 10mm2 1080p H.264/AVC High-Profile Encoder Chip. ISSCC 2008: 314-315 - 2007
- [c2]Chia-Chun Lin, Yu-Kun Lin, Tian-Sheuan Chang:
PMRME: A Parallel Multi-Resolution Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding. ICASSP (2) 2007: 385-388 - 2006
- [c1]Chia-Chun Lin, Yu-Kun Lin, Tian-Sheuan Chang:
A Fast Algorithm and Its Architecture for Motion Estimation in MPEG-4 AVC/H.264 Video Coding. APCCAS 2006: 1248-1251 - 2004
- [j1]Duan-Shin Lee, Chia-Chun Lin:
Window Adaptive TCP for EGPRS Networks. J. Inf. Sci. Eng. 20(5): 805-820 (2004)
Coauthor Index
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last updated on 2024-05-08 21:02 CEST by the dblp team
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