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Takanori Hayashida

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2010 – 2019

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2013
[c6]
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Ken Yano, Takanori Hayashida, Toshinori Sato:
Improving timing error tolerance without impact on chip area and power consumption. ISQED 2013: 373-378
2012
[j1]
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Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida:
A Selective Replacement Method for Timing-Error-Predicting flip-Flops. J. Circuits Syst. Comput. 21(6) (2012)
[c5]
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Toshinori Sato, Hideki Mori, Rikiya Yano, Takanori Hayashida:
Importance of Single-Core Performance in the Multicore Era. ACSC 2012: 107-114
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Toshinori Sato, Takanori Hayashida, Ken Yano:
Dynamically reducing overestimated design margin of MultiCores. HPCS 2012: 403-409
[c3]
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Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida:
Guidelines for mitigating NBTI degradation in on-chip memories. ISCIT 2012: 822-827
[c2]
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Ken Yano, Takanori Hayashida, Toshinori Sato:
Analysis of SER Improvement by Radiation Hardened Latches. PRDC 2012: 89-95
2011
[c1]
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  - conf/cisis/SatoYH11
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Toshinori Sato, Takahito Yoshiki, Takanori Hayashida:
Multicore Power Management Utilizing Error-Predicting Flip-flop. CISIS 2011: 606-611

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