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Journal Articles
- 2016
[j2]Omar Abdelfattah, George Gal, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih:
A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2050-2061 (2016)- 2015
- [j1]Omar Abdelfattah, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih:
An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2380-2390 (2015)
Conference and Workshop Papers
- 2015
- [c8]Omar Abdelfattah, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih:
A 0.35-V bulk-driven self-biased OTA with rail-to-rail input range in 65 nm CMOS. ISCAS 2015: 257-260 - [c7]Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts, Yi-Chi Shih:
A 0.55-V 1-GHz frequency synthesizer PLL for ultra-low-voltage ultra-low-power applications. LASCAS 2015: 1-4 - [c6]Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts, Yi-Chi Shih:
A 0.6V-supply bandgap reference in 65 nm CMOS. NEWCAS 2015: 1-4 - 2014
- [c5]Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts, Yi-Chi Shih:
Optimization of LC-VCO tuning range under different inductor/varactor losses limitations. CCECE 2014: 1-5 - 2013
- [c4]Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts:
A simple analog CMOS design tool using transistor dimension-independent parameters. ISCAS 2013: 1067-1070 - [c3]Omar Abdelfattah, Ishiang Shih, Gordon W. Roberts:
Analytical comparison between passive loop filter topologies for frequency synthesizer PLLs. NEWCAS 2013: 1-4 - 2012
- [c2]Marco Macedo, Gordon W. Roberts, Ishiang Shih:
Track and hold for Giga-sample ADC applications using CMOS technology. ISCAS 2012: 2725-2728 - 2010
- [c1]Guanghui Chang, Huawei Lu, Shuyu Chen, Ishiang Shih:
Grouping Fault Detection Protocol under Dynamic Network Environments. PDPTA 2010: 151-155
Coauthor Index
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