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2020 – today
- 2024
[c13]Ta Tan, Xiaowen Chen, Chen Li, Jianzhuang Lu:
Load balancing-oriented fault-tolerant NoC design. ITC-Asia 2024: 1-6- 2022
- [j4]Mingjie Wei
, Yunping Zhao, Xiaowen Chen, Chen Li, Jianzhuang Lu:
Towards Convolutional Neural Network Acceleration and Compression Based on Simonk-Means. Sensors 22(11): 4298 (2022) - [j3]Hanyan Liu, Xiaowen Chen, Yunping Zhao, Chen Li, Jianzhuang Lu:
TTQR: A Traffic- and Thermal-Aware Q-Routing for 3D Network-on-Chip. Sensors 22(22): 8721 (2022) - [c12]Wencai Gao, Xiaowen Chen, Chen Li, Jianzhuang Lu, Hanyan Liu:
HCER: A High Cost-Effectiveness Multi-Bit Fault-Tolerant NoC Router. HPCC/DSS/SmartCity/DependSys 2022: 1241-1248 - [c11]Mingjie Wei, Yunping Zhao, Jianzhuang Lu, Xiaowen Chen, Chen Li, Zerun Li:
Convolutional Neural Network Accelerator for Compression Based on Simon k-means. IJCNN 2022: 1-7 - 2021
- [c10]Yuekai Zhao, Jianzhuang Lu, Xiaowen Chen:
Accelerating Depthwise Separable Convolutions with Vector Processor. ICANN (2) 2021: 145-156 - [c9]Yuekai Zhao, Jianzhuang Lu, Xiaowen Chen:
Vectorized Winograd's algorithm for Convolution Neural networks. ISPA/BDCloud/SocialCom/SustainCom 2021: 715-722 - 2020
- [j2]Yunping Zhao, Jianzhuang Lu, Xiaowen Chen:
An Accelerator Design Using a MTCA Decomposition Algorithm for CNNs. Sensors 20(19): 5558 (2020) - [c8]Yunping Zhao, Jianzhuang Lu, Xiaowen Chen:
A Design of GEMM Parallel Computing Accelerator Based on Vector SIMD Technology. ICCTA 2020: 122-128 - [c7]Yunping Zhao, Xiaowen Chen, Rui Xu, Jinhui Wei, Jianzhuang Lu, Bo Yuan:
A Research and Design of Lightweight Convolutional Neural Networks Accelerator Based on Systolic Array Structure. ICRAI 2020: 241-247 - [c6]Jinhui Wei, Jianzhuang Lu, Qi Yu, Chen Li, Yunping Zhao:
Dynamic GMMU Bypass for Address Translation in Multi-GPU Systems. NPC 2020: 147-158
2010 – 2019
- 2015
- [c5]Xiaowen Chen, Zhonghai Lu, Yang Li, Axel Jantsch, Xueqian Zhao, Shuming Chen, Yang Guo, Zonglin Liu, Jianzhuang Lu, Jianghua Wan, Shuwei Sun, Shenggang Chen, Hu Chen:
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs. ISVLSI 2015: 398-403 - 2011
- [c4]Shuming Chen, Xiaowen Chen, Yi Xu, Jianghua Wan, Jianzhuang Lu, Xiangyuan Liu, Shenggang Chen:
Design and chip implementation of a heterogeneous multi-core DSP. ASP-DAC 2011: 91-92 - 2010
- [j1]Shuming Chen, Jianghua Wan, Jianzhuang Lu, Zhong Liu, Hai-Yan Sun, Yong-Jie Sun, Hengzhu Liu, Xiang-Yuan Liu, Zhentao Li, Yi Xu, Xiaowen Chen:
YHFT-QDSP: High-Performance Heterogeneous Multi-Core DSP. J. Comput. Sci. Technol. 25(2): 214-224 (2010) - [c3]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Jianzhuang Lu, Hucheng Wu:
Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique. ISVLSI 2010: 462-463
2000 – 2009
- 2004
- [c2]Jianzhuang Lu, Chunyuan Zhang, Zhiying Wang, Yun Cheng, Dan Wu:
A Case of SCMP with TLS. ISPA 2004: 975-984 - 2003
- [c1]Li Shen, Zhiying Wang, Jianzhuang Lu:
Predicate Analysis Based on Path Information. APPT 2003: 147-151
Coauthor Index
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