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ORCIDTomasz Grzes
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2020 – today
- 2024
[c19]Tomasz Grzes
:
Voice Long Distance Transmission Using Audio Codec for Low-Performance Microcontrollers and LoRa Communication for Use in IoT. CISIM 2024: 166-178- 2022
- [j7]Krzysztof Wolk, Agnieszka Wolk, Dominika Cecylia Wnuk, Tomasz Grzes, Ida Skubis:
Survey on dialogue systems including slavic languages. Neurocomputing 477: 62-84 (2022) - [j6]Maciej Kopczynski, Tomasz Grzes:
FPGA supported rough set reduct calculation for big datasets. J. Intell. Inf. Syst. 59(3): 779-799 (2022) - 2021
- [j5]Maciej Kopczynski, Tomasz Grzes:
Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets. J. Artif. Intell. Soft Comput. Res. 11(2): 99-110 (2021) - [c18]Michal Czolombitko, Tomasz Grzes, Maciej Kopczynski, Urszula Kuzelewska, Anna Lupinska-Dubicka, Dorota Mozyrska, Joanna Panasiuk:
Development of Digital Competences of Elementary School Teachers with a Life-Long Learning Approach. CISIM 2021: 100-111 - 2020
- [j4]Mateusz Choromanski, Tomasz Grzes, Piotr Honko:
Breadth search strategies for finding minimal reducts: towards hardware implementation. Neural Comput. Appl. 32(18): 14801-14816 (2020) - [c17]Valery Salauyou, Damian Borecki, Tomasz Grzes:
The Synthesis Method of High-Speed Finite State Machines in FPGA. CISIM 2020: 97-107 - [c16]Maciej Kopczynski, Tomasz Grzes:
Parallelized Hardware Rough Set Processor Architecture in FPGA for Core Calculation in Big Datasets. ICARCV 2020: 1098-1103
2010 – 2019
- 2019
- [c15]Mateusz Choromanski, Tomasz Grzes, Piotr Honko:
Two FPGA Devices in the Problem of Finding Minimal Reducts. CISIM 2019: 410-420 - [c14]Tomasz Grzes:
Lossless and Lossy Audio Codecs for Low-Performance Microcontrollers for Use in IoT. CISIM 2019: 433-444 - [c13]Tomasz Grzes, Maciej Kopczynski:
Hardware Implementation on Field Programmable Gate Array of Two-Stage Algorithm for Rough Set Reduct Generation. IJCRS 2019: 495-506 - 2018
- [c12]Tomasz Grzes:
Multiple Codes State Assignment and Code Length Reduction for Power Minimization of Finite State Machines. CISIM 2018: 341-353 - [c11]Damian Borecki, Valery Salauyou, Tomasz Grzes:
High-Speed Finite State Machine Design by State Splitting. DepCoS-RELCOMEX 2018: 64-73 - 2017
- [c10]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Hardware Supported Rule-Based Classification on Big Datasets. IJCRS (1) 2017: 655-668 - 2016
- [j3]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Core for Large Datasets: Rough Sets on FPGA. Fundam. Informaticae 147(2-3): 241-259 (2016) - [j2]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Rough Sets Based LEM2 Rules Generation Supported by FPGA. Fundam. Informaticae 148(1-2): 107-122 (2016) - [c9]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Hardware Supported Rough Sets Based Rules Generation for Big Datasets. CISIM 2016: 91-102 - 2015
- [c8]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Core for Large Datasets: Rough Sets on FPGA. CS&P 2015: 235-246 - [c7]Adam Klimowicz, Valery Solov'ev, Tomasz Grzes:
Minimization Method of Finite State Machines for Low Power Design. DSD 2015: 259-262 - [c6]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Computation of Cores in Big Datasets: An FPGA Approach. RSKT 2015: 153-163 - 2014
- [c5]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Generating Core in Rough Set Theory: Design and Implementation on FPGA. RSEISP 2014: 209-216 - [c4]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
FPGA in Rough-Granular Computing: Reduct Generation. WI-IAT (1) 2014: 364-370 - 2013
- [j1]Jaroslaw Stepaniuk, Maciej Kopczynski, Tomasz Grzes:
The First Step Toward Processor for Rough Set Methods. Fundam. Informaticae 127(1-4): 429-443 (2013) - [c3]Marek Parfieniuk, Tomasz Lukaszuk, Tomasz Grzes:
A Scalable Distributed Architecture for Emulating Unreliable Networks for Testing Multimedia Systems. IP&C 2013: 309-316 - [c2]Tomasz Grzes, Maciej Kopczynski, Jaroslaw Stepaniuk:
FPGA in Rough Set Based Core and Reduct Computation. RSKT 2013: 263-270
2000 – 2009
- 2007
- [c1]Valery Salauyou, Tomasz Grzes:
FSM State Assignment Methods for Low-Power Design. CISIM 2007: 345-350
Coauthor Index
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last updated on 2024-09-21 23:40 CEST by the dblp team
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