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2020 – today
- 2022
[j8]Ireneusz Mrozek, Nikolai A. Shevchenko, Vyacheslav N. Yarmolik:
Universal Address Sequence Generator for Memory Built-in Self-test. Fundam. Informaticae 188(1): 41-61 (2022)- [i1]Ireneusz Mrozek, Nikolai A. Shevchenko, Vyacheslav N. Yarmolik:
Universal Address Sequence Generator for Memory Built-in Self-test. CoRR abs/2208.05325 (2022) - 2021
- [j7]Ireneusz Mrozek
, Vyacheslav N. Yarmolik:
Transparent Memory Tests Based on the Double Address Sequences. Entropy 23(7): 894 (2021)
2010 – 2019
- 2018
- [c7]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Pseudo-Exhaustive Random Access Memory Testing Based on March Tests with Random Background Variation. EWDTS 2018: 1-8 - 2017
- [j6]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Two-Run RAM March Testing with Address Decimation. J. Circuits Syst. Comput. 26(2): 1750031:1-1750031:17 (2017) - [c6]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Optimal Controlled Random Tests. CISIM 2017: 27-38 - 2016
- [j5]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Multiple Controlled Random Testing. Fundam. Informaticae 144(1): 23-43 (2016) - [c5]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Methods of Synthesis of Controlled Random Tests. CISIM 2016: 429-440 - 2015
- [j4]Vyacheslav N. Yarmolik, Ireneusz Mrozek, Svetlana V. Yarmolik:
Controlled method of random test synthesis. Autom. Control. Comput. Sci. 49(6): 395-403 (2015) - 2013
- [c4]Ireneusz Mrozek, Svetlana V. Yarmolik:
Analyses of two run march tests with address decimation for BIST procedure. EWDTS 2013: 1-4 - 2012
- [j3]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Iterative Antirandom Testing. J. Electron. Test. 28(3): 301-315 (2012) - [j2]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Antirandom Test Vectors for BIST in Hardware/Software Systems. Fundam. Informaticae 119(2): 163-185 (2012) - 2010
- [j1]Ireneusz Mrozek:
Analysis of multibackground memory testing techniques. Int. J. Appl. Math. Comput. Sci. 20(1): 191-205 (2010)
2000 – 2009
- 2008
- [c3]Ireneusz Mrozek, Vyacheslav N. Yarmolik, Eugenia Buslowska:
Multi Background Memory Testing. CISIM 2008: 155-156 - [c2]Ireneusz Mrozek, Vyacheslav N. Yarmolik:
Optimal Backgrounds Selection for Multi Run Memory Testing. DDECS 2008: 332-338 - 2007
- [c1]S. V. Yarmolik, Ireneusz Mrozek, Bartosz Sokol:
Address Sequences Generation for Multiple Run Memory Testing. CISIM 2007: 341-344 - 2005
- [p1]Bartosz Sokol, Ireneusz Mrozek, Wiaczeslaw Yarmolik:
Impact of the address changing on the detection of pattern sensitive faults. Information Processing and Security Systems 2005: 217-225
Coauthor Index
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