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ORCIDJean-Luc Beuchat
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2020 – today
- 2023
[i21]Jean-Luc Beuchat, Valon Rexhepi:
A Digital Identity in the Hands of Swiss Citizens. IACR Cryptol. ePrint Arch. 2023: 1099 (2023)
2010 – 2019
- 2017
- [j12]Nuray At, Jean-Luc Beuchat
, Eiji Okamoto, Ismail San, Teppei Yamazaki:
A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl. J. Parallel Distributed Comput. 106: 106-120 (2017) - 2016
- [j11]Mehran Mozaffari Kermani, Reza Azarderakhsh, Kui Ren, Jean-Luc Beuchat:
Guest Editorial: Introduction to the Special Section on Emerging Security Trends for Biomedical Computations, Devices, and Infrastructures. IEEE ACM Trans. Comput. Biol. Bioinform. 13(3): 399-400 (2016) - 2014
- [j10]Nuray At, Jean-Luc Beuchat, Eiji Okamoto, Ismail San, Teppei Yamazaki:
Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(2): 485-498 (2014) - 2013
- [i20]Nuray At, Jean-Luc Beuchat, Eiji Okamoto, Ismail San, Teppei Yamazaki:
Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA. IACR Cryptol. ePrint Arch. 2013: 113 (2013) - 2012
- [c20]Diego F. Aranha, Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals:
Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves. CT-RSA 2012: 98-115 - [c19]Nuray At, Jean-Luc Beuchat, Ismail San:
Compact Implementation of Threefish and Skein on FPGA. NTMS 2012: 1-5 - [i19]Nuray At, Jean-Luc Beuchat, Ismail San:
Compact Implementation of Threefish and Skein on FPGA. IACR Cryptol. ePrint Arch. 2012: 126 (2012) - [i18]Nuray At, Jean-Luc Beuchat, Eiji Okamoto, Ismail San, Teppei Yamazaki:
A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function Grøstl. IACR Cryptol. ePrint Arch. 2012: 535 (2012) - 2011
- [j9]Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki:
A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO. J. Cryptogr. Eng. 1(2): 101-121 (2011) - [j8]Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez:
Fast Architectures for the \eta_T Pairing over Small-Characteristic Supersingular Elliptic Curves. IEEE Trans. Computers 60(2): 266-281 (2011) - [i17]Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki:
A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO. IACR Cryptol. ePrint Arch. 2011: 78 (2011) - 2010
- [j7]Jean-Luc Beuchat, Hiroshi Doi, Kaoru Fujita, Atsuo Inomata, Piseth Ith, Akira Kanaoka, Masayoshi Katouno, Masahiro Mambo, Eiji Okamoto, Takeshi Okamoto, Takaaki Shiga, Masaaki Shirase, Ryuji Soga, Tsuyoshi Takagi, Ananda Vithanage, Hiroyasu Yamamoto:
FPGA and ASIC implementations of the etaT pairing in characteristic three. Comput. Electr. Eng. 36(1): 73-87 (2010) - [c18]Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki:
Compact implementations of BLAKE-32 and BLAKE-64 on FPGA. FPT 2010: 170-177 - [c17]Jean-Luc Beuchat, Jorge Enrique González-Díaz, Shigeo Mitsunari, Eiji Okamoto, Francisco Rodríguez-Henríquez, Tadanori Teruya:
High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves. Pairing 2010: 21-39 - [i16]Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki:
Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA. IACR Cryptol. ePrint Arch. 2010: 173 (2010) - [i15]Jean-Luc Beuchat, Jorge Enrique González-Díaz, Shigeo Mitsunari, Eiji Okamoto, Francisco Rodríguez-Henríquez, Tadanori Teruya:
High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves. IACR Cryptol. ePrint Arch. 2010: 354 (2010) - [i14]Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki:
A Compact FPGA Implementation of the SHA-3 Candidate ECHO. IACR Cryptol. ePrint Arch. 2010: 364 (2010) - [i13]Diego F. Aranha, Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals:
Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves. IACR Cryptol. ePrint Arch. 2010: 559 (2010)
2000 – 2009
- 2009
- [c16]Jean-Luc Beuchat, Emmanuel López-Trejo, Luis Martínez-Ramos, Shigeo Mitsunari, Francisco Rodríguez-Henríquez:
Multi-core Implementation of the Tate Pairing over Supersingular Elliptic Curves. CANS 2009: 413-432 - [c15]Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez:
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers. CHES 2009: 225-239 - [i12]Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez:
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers. IACR Cryptol. ePrint Arch. 2009: 122 (2009) - [i11]Jean-Luc Beuchat, Emmanuel López-Trejo, Luis Martínez-Ramos, Shigeo Mitsunari, Francisco Rodríguez-Henríquez:
Multi-core Implementation of the Tate Pairing over Supersingular Elliptic Curves. IACR Cryptol. ePrint Arch. 2009: 276 (2009) - [i10]Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez:
Fast Architectures for the etaT Pairing over Small-Characteristic Supersingular Elliptic Curves. IACR Cryptol. ePrint Arch. 2009: 398 (2009) - 2008
- [j6]Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Masaaki Shirase, Tsuyoshi Takagi:
Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three. IEEE Trans. Computers 57(11): 1454-1468 (2008) - [j5]Jean-Luc Beuchat, Jean-Michel Muller:
Automatic Generation of Modular Multipliers for FPGA Applications. IEEE Trans. Computers 57(12): 1600-1613 (2008) - [c14]Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Francisco Rodríguez-Henríquez:
A Comparison between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m. Pairing 2008: 297-315 - [i9]Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Francisco Rodríguez-Henríquez:
A Comparison Between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m. IACR Cryptol. ePrint Arch. 2008: 115 (2008) - [i8]Nidia Cortez-Duarte, Francisco Rodríguez-Henríquez, Jean-Luc Beuchat, Eiji Okamoto:
A Pipelined Karatsuba-Ofman Multiplier over GF(397) Amenable for Pairing Computation. IACR Cryptol. ePrint Arch. 2008: 127 (2008) - [i7]Jean-Luc Beuchat, Hiroshi Doi, Kaoru Fujita, Atsuo Inomata, Piseth Ith, Akira Kanaoka, Masayoshi Katouno, Masahiro Mambo, Eiji Okamoto, Takeshi Okamoto, Takaaki Shiga, Masaaki Shirase, Ryuji Soga, Tsuyoshi Takagi, Ananda Vithanage, Hiroyasu Yamamoto:
FPGA and ASIC Implementations of the etaT Pairing in Characteristic Three. IACR Cryptol. ePrint Arch. 2008: 280 (2008) - 2007
- [c13]Jean-Luc Beuchat, Takanori Miyoshi, Yoshihito Oyama, Eiji Okamoto:
Multiplication over Fpm on FPGA: A Survey. ARC 2007: 214-225 - [c12]Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto:
An Algorithm for the nt Pairing Calculation in Characteristic Three and its Hardware Implementation. IEEE Symposium on Computer Arithmetic 2007: 97-104 - [c11]Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto:
Arithmetic Operators for Pairing-Based Cryptography. CHES 2007: 239-255 - [c10]Jean-Luc Beuchat, Nicolas Brisebarre, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto:
A Coprocessor for the Final Exponentiation of the eta T Pairing in Characteristic Three. WAIFI 2007: 25-39 - [i6]Jean-Luc Beuchat:
Further Comments on "Residue-to-Binary Converters Based on New Chinese Remainder Theorems". CoRR abs/0707.3732 (2007) - [i5]Jean-Luc Beuchat, Nicolas Brisebarre, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto:
A Coprocessor for the Final Exponentiation of the etaT Pairing in Characteristic Three. IACR Cryptol. ePrint Arch. 2007: 45 (2007) - [i4]Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto:
Arithmetic Operators for Pairing-Based Cryptography. IACR Cryptol. ePrint Arch. 2007: 91 (2007) - [i3]Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto:
A Refined Algorithm for the etaT Pairing Calculation in Characteristic Three. IACR Cryptol. ePrint Arch. 2007: 311 (2007) - [i2]Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Masaaki Shirase, Tsuyoshi Takagi:
Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three. IACR Cryptol. ePrint Arch. 2007: 417 (2007) - 2006
- [i1]Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto:
An Algorithm for the ηT Pairing Calculation in Characteristic Three and its Hardware Implementation. IACR Cryptol. ePrint Arch. 2006: 327 (2006) - 2005
- [c9]Jean-Luc Beuchat, Jean-Michel Muller:
Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement. ASAP 2005: 303-308 - 2004
- [j4]Jean-Luc Beuchat, Arnaud Tisserand:
Évaluation polynomiale en-ligne de fonctions élémentaires sur FPGA. Tech. Sci. Informatiques 23(10): 1247-1267 (2004) - 2003
- [c8]Jean-Luc Beuchat:
Modular Multiplication for FPGA Implementation of the IDEA Block Cipher. ASAP 2003: 412-422 - [c7]Jean-Luc Beuchat:
FPGA Implementations of the RC6 Block Cipher. FPL 2003: 101-110 - [c6]Jean-Luc Beuchat:
Some Modular Adders and Multipliers for Field Programmable Gate Arrays. IPDPS 2003: 190 - 2002
- [j3]Jean-Luc Beuchat, Jacques-Olivier Haenni, Héctor Fabio Restrepo, Christof Teuscher, Francisco J. Gómez, Eduardo Sanchez:
Approches matérielles et logicielles de l'algorithme de chiffrement IDEA. Tech. Sci. Informatiques 21(2): 203-224 (2002) - [c5]Jean-Luc Beuchat, Arnaud Tisserand:
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices. FPL 2002: 513-522 - 2000
- [j2]Jean-Luc Beuchat, Jacques-Olivier Haenni:
Von Neumann's 29-state cellular automaton: a hardware implementation. IEEE Trans. Educ. 43(3): 300-308 (2000)
1990 – 1999
- 1999
- [j1]Eduardo Sanchez, Moshe Sipper, Jacques-Olivier Haenni, Jean-Luc Beuchat, André Stauffer, Andrés Pérez-Uribe:
Static and Dynamic Configurable Systems. IEEE Trans. Computers 48(6): 556-564 (1999) - [c4]Jean-Luc Beuchat, Eduardo Sanchez:
An On-Line Arithmetic-Based Reconfigurable Neuroprocessor. IPPS/SPDP Workshops 1999: 700-702 - [c3]Jean-Luc Beuchat, Eduardo Sanchez:
Using On-Line Arithmetic and Reconfiguration for Neuroprocessor Implementations. IWANN (2) 1999: 129-138 - 1998
- [c2]Jacques-Olivier Haenni, Jean-Luc Beuchat, Eduardo Sanchez:
RENCO: A Reconfigurable Network Computer. FCCM 1998: 288-289 - [c1]Jean-Luc Beuchat, Jacques-Olivier Haenni, Eduardo Sanchez:
Hardware Reconfigurable Neural Networks. IPPS/SPDP Workshops 1998: 91-98
Coauthor Index
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