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ORCIDM. Nirmala Devi 0001
Person information
- affiliation: Amrita School of Engineering, Department of Electronics and Communication Engineering, Coimbatore, India
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2020 – today
- 2023
[j10]C. Sahana, Nirmala Devi Manickam
, M. Jayakumar:
Hexagonal-Triangular Combinatorial Structure Based Dual-Band Circularly Polarized Patch Antenna for GAGAN Receivers. IEEE Access 11: 23205-23216 (2023)- [j9]Shiny Mukkath I., Nirmala Devi M.:
PUF based on chip comparison technique for trustworthy scan design data security against side channel attack. Int. J. Cloud Comput. 12(2/3/4): 201-223 (2023) - [j8]Karthigha Balamurugan, M. Nirmala Devi, M. Jayakumar:
Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors. J. Electr. Comput. Eng. 2023: 2469673:1-2469673:15 (2023) - [c17]Vaishnavi Sankar, Balachander Sathianarayanan, Nirmala Devi Manickam, M. Jayakumar:
Reliability Enhancement of Hardware Trojan Detection using Histogram Augmentation Technique. VLSID 2023: 365-370 - 2022
- [j7]Vaishnavi Sankar, M. Nirmala Devi, M. Jayakumar:
Data Augmented Hardware Trojan Detection Using Label Spreading Algorithm Based Transductive Learning for Edge Computing-Assisted IoT Devices. IEEE Access 10: 102789-102803 (2022) - [j6]Balachander Sathianarayanan, Yogesh Chandra Singh Samant, Prahalad S. Conjeepuram Guruprasad, Varshin B. Hariharan, Nirmala Devi Manickam:
Feature-based augmentation and classification for tabular data. CAAI Trans. Intell. Technol. 7(3): 481-491 (2022) - [j5]M. I. Shiny, M. Nirmala Devi:
Trustworthy Scan Design and Testability Using Obfuscation and Logic Locking Scheme for Wireless Network Application. Mob. Networks Appl. 27(3): 1000-1018 (2022) - [c16]Paul Anu, N. Mohankumar, M. Nirmala Devi:
Obviating Multiple Attacks with Enhanced Logic Locking. IC3 2022: 162-167 - 2021
- [j4]M. Ganesan, R. Lavanya, M. Nirmala Devi:
Fault detection in satellite power system using convolutional neural network. Telecommun. Syst. 76(4): 505-511 (2021)
2010 – 2019
- 2019
- [j3]R. Sree Ranjani, M. Nirmala Devi:
Secured Hardware Design with Locker-Box Against a Key-Guessing Attacks. J. Low Power Electron. 15(2): 246-255 (2019) - [c15]M. Priyatharishini, M. Nirmala Devi:
Realization of Re-configurable True Random Number Generator on FPGA. SSCC 2019: 247-256 - 2018
- [j2]Arun Kumar Sundar Rajan, Armin Feucht, Lothar Gamer, Idriz Smaili, M. Nirmala Devi:
Hypervisor for consolidating real-time automotive control units: Its procedure, implications and hidden pitfalls. J. Syst. Archit. 82: 37-48 (2018) - [c14]S. Jaiyant Gopal, J. Ramnarayan, S. Kirthiga, M. Jayakumar, M. Nirmala Devi, R. Gandhiraj, Subhash Chandra Bera:
Capacity Analysis of Correlated MIMO in GEOSAT Downlink Land Mobile System. ICACCI 2018: 1594-1600 - [c13]Sree Ranjani Rajendran, M. Nirmala Devi:
A Novel Logical Locking Technique Against Key-Guessing Attacks. ISED 2018: 178-182 - [c12]Sivappriya Manivannan, N. Nalla Anandakumar, M. Nirmala Devi:
Key Retrieval from AES Architecture Through Hardware Trojan Horse. SSCC 2018: 483-494 - [c11]Bandarupalli Chandini, M. Nirmala Devi:
Analysis of Circuits for Security Using Logic Encryption. SSCC 2018: 520-528 - [c10]Sree Ranjani Rajendran, M. Nirmala Devi:
Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks. VDAT 2018: 186-197 - 2017
- [j1]Rajat Subhra Chakraborty, Samuel Pagliarini, Jimson Mathew, Sree Ranjani Rajendran, M. Nirmala Devi:
A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis. IEEE Trans. Emerg. Top. Comput. 5(2): 260-270 (2017) - [c9]K. Atchuta Sashank, Hari Sivarami Reddy, P. Pavithran, M. S. Akash, M. Nirmala Devi:
Hardware Trojan Detection Using Effective Test Patterns and Selective Segmentation. SSCC 2017: 379-386 - 2015
- [c8]R. Bharath, G. Arun Sabari, Dhinesh Ravi Krishna, Arun Prasathe, K. Harish, N. Mohankumar, M. Nirmala Devi:
Malicious Circuit Detection for Improved Hardware Security. SSCC 2015: 464-472 - [c7]Eknadh Vaddi, Karthik Gaddam, Rahul Karthik Maniam, Sai Abhishek Mallavajjala, Srinivasulu Dasari, M. Nirmala Devi:
Detection and Diagnosis of Hardware Trojan Using Power Analysis. SSCC 2015: 519-529 - 2014
- [c6]Ramesh Bhakthavatchalu, Sreeja Krishnan, V. Vineeth, M. Nirmala Devi:
Deterministic seed selection and pattern reduction in Logic BIST. VDAT 2014: 1-2 - [c5]S. Sarathkrishna, Karthigha Balamurugan, M. Nirmala Devi, M. Jayakumar:
Design and analysis of GaN HEMT based LNA with CPW matching. WOCN 2014: 1-4 - 2012
- [c4]P. R. Sruthi, M. Nirmala Devi:
A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power. VDAT 2012: 198-208 - 2010
- [c3]Nisha Haridas, M. Nirmala Devi:
PSO learning on artificial neural networks. A2CWiC 2010: 3:1-3:6
2000 – 2009
- 2008
- [c2]N. Mohankumar, B. Bhuvan, M. Nirmala Devi, S. Arumugam:
A Modified Genetic Algorithm for Evolution of Neural Network in Designing an Evolutionary Neuro-Hardware. GEM 2008: 108-111 - [c1]Venakata Saichand, M. Nirmala Devi, S. Arumugam, N. Mohankumar:
FPGA Realization of Activation Function for Artificial Neural Networks. ISDA (3) 2008: 159-164
Coauthor Index
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