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ORCIDHajime Shibata
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2020 – today
- 2024
[j14]Rishabh Mittal
, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee:
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. IEEE J. Solid State Circuits 59(4): 1158-1170 (2024)- [c18]Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Qingnan Yu, Zhao Li, Zeynep Lulec, Konstantinos Vasilakopoulos, Prawal Shrestha, Donald Paterson, Raviteja Theertham, Aseer Chowdhury:
22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors. ISSCC 2024: 390-392 - 2023
- [c17]Sharvil Patil, Raviteja Theertham, Hajime Shibata, Victor Kozlov, Asha Ganesan, Efram Burlingame, Zhao Li, Rama Thakar, Qianqian Zhang, Yue Yin, Aathreya S. Bhat:
A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs. CICC 2023: 1-2 - [c16]Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee:
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j13]Mohammed Wagih Ismail, Hajime Shibata, Zhao Li, Sharvil Patil, Tony Chan Carusone:
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4731-4740 (2022) - 2021
- [j12]Shanthi Pavan, Hajime Shibata:
Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 810-815 (2021) - 2020
- [c15]Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya S. Bhat, Shanthi Pavan:
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. ISSCC 2020: 260-262
2010 – 2019
- 2018
- [j11]Qiwei Wang, Hajime Shibata, Antonio Liscidini, Anthony Chan Carusone:
A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers. IEEE J. Solid State Circuits 53(3): 681-691 (2018) - [j10]Jialin Zhao, Yunzhi Dong, Wenhua Yang, Hajime Shibata, Prawal Shrestha, Zhao Li, Trevor C. Caldwell, José B. Silva, Jeffrey C. Gealow:
A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique. IEEE Trans. Circuits Syst. II Express Briefs 65-II(7): 859-863 (2018) - [c14]Yunzhi Dong, José B. Silva, Qingdong Meng, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Donald Paterson, Jeffrey C. Gealow:
Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS. CICC 2018: 1-4 - [c13]Hajime Shibata:
Thermal noise limits - ΔΣ vs. pipeline ADCs. ISCAS 2018: 1 - 2017
- [j9]Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil, Shanthi Pavan:
A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD. IEEE J. Solid State Circuits 52(12): 3219-3234 (2017) - [c12]Yunzhi Dong, José B. Silva, Qingdong Meng, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Donald Paterson, Jeffrey C. Gealow:
Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS. CICC 2017: 1-4 - [c11]Qiwei Wang, Hajime Shibata, Anthony Chan Carusone, Antonio Liscidini:
A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS. CICC 2017: 1-4 - [c10]Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson:
16.2 A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving -161dBFS/Hz NSD. ISSCC 2017: 278-279 - [c9]Trevor C. Caldwell, Hajime Shibata:
High-speed oversampled continuous-time analog-to-digital converters. MWSCAS 2017: 1001-1004 - 2016
- [j8]Yunzhi Dong, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Richard Schreier, Qingdong Meng, José B. Silva, Donald Paterson, Jeffrey C. Gealow:
A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS. IEEE J. Solid State Circuits 51(12): 2917-2927 (2016) - [c8]Yunzhi Dong, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Richard Schreier, Qingdong Meng, José B. Silva, Donald Paterson, Jeffrey C. Gealow:
15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS. ISSCC 2016: 278-279 - 2014
- [c7]Trevor C. Caldwell, David Alldred, Richard Schreier, Hajime Shibata, Yunzhi Dong:
Advances in high-speed continuous-time delta-sigma modulators. CICC 2014: 1-8 - 2012
- [j7]Hajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai:
A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz Using 550 mW. IEEE J. Solid State Circuits 47(12): 2888-2897 (2012) - [c6]Hajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai:
A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW. ISSCC 2012: 150-152 - 2010
- [j6]Shunsuke Okura, Hajime Shibata, Tetsuro Okura, Toru Ido, Kenji Taniguchi:
A Frequency Model of a Continuously Driven Clocked CMOS Comparator. IEEE Trans. Circuits Syst. II Express Briefs 57-II(12): 956-960 (2010)
2000 – 2009
- 2008
- [c5]Wenhua Yang, William Schofield, Hajime Shibata, Sudhir Korrapati, Ali Shaikh, Nazmy Abaskharoun, Dave Ribner:
A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD. ISSCC 2008: 498-499 - 2007
- [j5]Hiromi Kashiwaya, Tetsuro Matsumoto, Hajime Shibata, Kiyoe Tani, Satoshi Kashiwaya:
Measurement System for Switching Current Distribution in Intrinsic Josephson Junctions. IEICE Trans. Electron. 90-C(3): 605-606 (2007) - 2006
- [j4]Richard Schreier, Nazmy Abaskharoun, Hajime Shibata, Donald Paterson, Steven Rose, Iuri Mehr, Qui Luu:
A 375-mW Quadrature Bandpass$\Delta\Sigma$ADC With 8.5-MHz BW and 90-dB DR at 44 MHz. IEEE J. Solid State Circuits 41(12): 2632-2640 (2006) - [c4]Shunsuke Okura, Tetsuro Okura, Kenji Taniguchi, Hajime Shibata:
Frequency Response Analysis of Latch Utilized in High-Speed Comparator. ICECS 2006: 1077-1080 - [c3]Richard Schreier, Nazmy Abaskharoun, Hajime Shibata, Iuri Mehr, Steve Rose, Donald Paterson:
A 375mW Quadrature Bandpass ΔΣ ADC with 90dB DR and 8.5MHz BW at 44MHz. ISSCC 2006: 141-150 - 2004
- [j3]Hajime Shibata, Adrian Stoica, Nobuo Fujii:
Controllable decoding for automated analog circuit structure design. Soft Comput. 8(5): 344-353 (2004) - 2003
- [j2]Hajime Shibata, Soji Mori, Nobuo Fujii:
Automated Design of Analog Circuits Using a Cell-Based Structure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(2): 364-370 (2003) - 2002
- [c2]Hajime Shibata, Soji Mori, Nobuo Fujii:
Automated Design of Analog Circuits Using Cell-Based Structure . Evolvable Hardware 2002: 85-92 - 2001
- [c1]Hajime Shibata, Nobuo Fujii:
Analog circuit synthesis by superimposing of sub-circuits. ISCAS (5) 2001: 427-430 - 2000
- [j1]Akira Nakaaki, Hajime Shibata, Toru Murase, Masahiko Tsukamoto, Shojiro Nishio:
Maintenance of location-dependent views in mobile database environments. Syst. Comput. Jpn. 31(11): 70-81 (2000)
Coauthor Index
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