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Yasuyuki Matsuya
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2020 – today
- 2021
- [j12]Yuji Inagaki, Yasuyuki Matsuya:
A Method for Detecting Timing of Photodiode Saturation without In-Pixel TDC for High-Dynamic-Range CMOS Image Sensor. IEICE Trans. Electron. 104-C(10): 607-616 (2021)
2010 – 2019
- 2017
- [j11]Yuji Inagaki, Yusaku Sugimori, Eri Ioka, Yasuyuki Matsuya:
A Logarithmic Compression ADC Using Transient Response of a Comparator. IEICE Trans. Electron. 100-C(4): 359-362 (2017) - 2016
- [j10]Eri Ioka, Nozomi Watanabe, Ryo Makishima, Yasuyuki Matsuya:
Noise Characteristic of the Chaotic Double Loop Delta Sigma Modulator. Int. J. Bifurc. Chaos 26(11): 1650178:1-1650178:8 (2016) - 2015
- [j9]Shizuka Bando, Akio Nozawa, Yasuyuki Matsuya:
Causal analysis between vehicle operating data and physiological responses. Artif. Life Robotics 20(4): 299-304 (2015) - 2011
- [j8]Yasuyuki Matsuya:
FOREWORD. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(2): 555 (2011)
2000 – 2009
- 2009
- [j7]Yasuyuki Matsuya, Takahiro Mesuda:
A Stereo Transmission Technique Using PDM Data and Synchronized Clock Channels. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2): 456-458 (2009) - 2005
- [j6]Jun Terada, Yasuyuki Matsuya, Shin'ichiro Mutoh, Yuichi Kado
:
A 1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks. IEICE Trans. Electron. 88-C(4): 479-483 (2005) - 2003
- [j5]Jun Terada, Yasuyuki Matsuya, Fumiharu Morisawa, Yuichi Kado:
8-mW, 1-V, 100-MSample/s, 6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(2): 313-317 (2003)
1990 – 1999
- 1997
- [j4]Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada:
A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. IEEE J. Solid State Circuits 32(6): 861-869 (1997) - 1996
- [j3]Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada:
A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application. IEEE J. Solid State Circuits 31(11): 1795-1802 (1996) - 1995
- [j2]Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya, Takahko Aoki, Satoshi Shigematsu, Junzo Yamada:
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE J. Solid State Circuits 30(8): 847-854 (1995) - 1994
- [j1]Yasuyuki Matsuya, Junzo Yamada:
1 V power supply, low-power consumption A/D conversion technique with swing-suppression noise shaping. IEEE J. Solid State Circuits 29(12): 1524-1530 (1994)
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