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ORCIDEric Karl
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2020 – today
- 2024
[c23]Daeyeon Kim, Yusung Kim, Ayush Shrivastava, Gyusung Park, Anandkumar Mahadevan Pillai, Kunal Bannore, Tri Doan, Muktadir Rahman, Gwanghyeon Baek, Clifford Ong, Xiaofei Wang, Zheng Guo, Eric Karl:
15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia. ISSCC 2024: 278-280- [c22]Walid M. Hafez, D. Abanulo, M. Abdelkader, S. An, C. Auth, D. Bahr, V. Balakrishnan, R. Bambery, M. Beck, M. Bhargava, S. Bhowmick, J. Biggs-houck, J. Birdsall, D. Caselli, H.-Y. Chang, Y. Chang, R. Chaudhuri, S. Chauhan, C. Chen, V. Chikarmane, K. Chikkadi, T. Chu, C. Connor, R. De Alba, Y. Deng, C. Destefano, D. Diana, Y. Dong, P. Elfick, Tyler Elko-Hansen, B. Fallahazad, Y. Fang, D. Gala, D. Garg, C. Geppert, S. Govindaraju, W. Grimm, H. Grunes, L. Guler, Z. Guo, A. Gupta, M. Hattendorf, S. Havelia, J. Hazra, A. Islam, A. Jain, S. Jaloviar, M. Jamil, M. Jang, M. Kabir, J. Kameswaran, Eric Karl, S. Kelgeri, A. Kennedy, C. Kilroy, J. Kim, Y. Kim, D. Krishnan, G. Lee, H.-P. Lee, Q. Li, H. Lin, A. Luk, Y. Luo, P. Macfarlane, A. Mamun, K. Marla, D. Mayeri, E. Mckenna, A. Miah, K. Mistry, M. Mleczko, S. Moon, D. Nardi, S. Natarajan, J. Nathawat, C. Nolph, C. Nugroho, P. Nyhus, A. Oni, P. Packan, D. Pak, A. Paliwal, R. Pandey, I. Paredes, K. Park, L. Paulson, A. Pierre, P. Plekhanov, C. Prasad, R. Ramaswamy, J. Riley, Johann Rode, R. Russell, S. Ryu, H. Saavedra, T. Salisbury, Justin Sandford, F. Shah, K. Shang, P. Shekhar, A. Shu, E. Skoug, J. Sohn, J. Song, M. Sprinkle, J. Su, A. Tan, T. Troeger, R. Tsao, A. Vaidya, C. Wallace, X. Wang, H. Wang, C. Ward, S. Wickramaratne, M. Wills, T. Wu, Z. Xia-hua, S. Xu, P. Yashar, J. Yaung, Y. Yu, M. Zilm, Bernhard Sell:
An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j13]Yusung Kim
, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl:
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology. IEEE J. Solid State Circuits 58(4): 1087-1093 (2023) - [c21]M. Shamanna, E. Abuayob, G. Aenuganti, C. Alvares, J. Antony, A. Bahudhanam, A. Chandran, P. Chew, A. Chatterjee, B. Chauhan, N. Dandeti, J. Desai, M. Doyle, T. Dmukauskas, P. Farache, E. Fetzer, K. Fischer, P. Hack, Y. Greenzweig, John Giacobbe, Walid M. Hafez, E. Haralson, A. Hegde, A. Illa, M. Islam, S. Jain, M. Jang, J. Nguyen, T. Tong, L. Jiang, Eric Karl, P. Kalangi, G. Khoo, A. Krishnamoorthy, B. Kuns, W. Li, R. Livengood, T. Malik, R. Priyanka, H. Faraby, Y. Maymon, K. Mistry, K. Morgan, S. Natarajan, O. Nevo, M. Oh, P. Pardy, J. Park, P. Penmatsa, Boyd Phelps, C. Peterson, S. Rajappa, A. Raveh, A Rezaie, T. Ravishankar, R. Ramaswamy, S. Reddy, R. Saha, S. Sen, R. Sanchez, R. Sanaga, B. Simkhovich, Bernhard Sell, M. Senger, B. Schnarch, M. Seshadri, O. Sidorov, S. Subramanian, K. Subramanian, B. Truong, S. Bangalore, Jeffery Hicks, S. Venkatesh, D. Christensen, K. Bhargav, M. Von Haartman, P. Joshi, S. Zickel, C.-H. Lin, J. Huening, T.-H. Wu, N. Bakken, A. Afzal, A. Raman, Sj. Rao, V. Kawar, J. Neirynck, D. Bradley, M. Duwe, S. Wu, V. Patil, M. Bayoumy:
E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c20]Wilfred Gomes, Altug Koker, Patrick N. Stover, Doug B. Ingerly, Scott Siers, Srikrishnan Venkataraman, Chris Pelto, Tejas Shah, Amreesh Rao, Frank O'Mahony, Eric Karl, Lance Cheney, Iqbal Rajwani, Hemant Jain, Ryan Cortez, Arun Chandrasekhar, Basavaraj Kanthi, Raja Koduri:
Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing. ISSCC 2022: 42-44 - [c19]Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni:
A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology. VLSI Technology and Circuits 2022: 136-137 - [c18]Yusung Kim, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl:
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology. VLSI Technology and Circuits 2022: 212-213 - 2021
- [j12]Friedel Gerfers, Ping-Hsuan Hsieh, Dejan Markovic, Jun Deguchi, Eric Karl:
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 56(1): 3-6 (2021) - [j11]Ravi R. Iyer, Vivek De, Ramesh Illikkal, David A. Koufaty, Bhushan Chitlur, Andrew Herdrich, Muhammad M. Khellah, Fatih Hamzaoglu, Eric Karl:
Advances in Microprocessor Cache Architectures Over the Last 25 Years. IEEE Micro 41(6): 78-88 (2021) - [c17]Eric Karl, Shinichiro Shiratake, Jonathan Chang:
Session 24 Overview: Advanced Embedded Memories Memory Subcommittee. ISSCC 2021: 332-333 - [c16]Christopher Gonzalez, Huichu Liu, Mijung Noh, Eric Karl, Thomas Toifl, Shawn S. H. Hsu:
F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets. ISSCC 2021: 529-532 - [c15]Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag:
SE1: What Technologies Will Shape the Future of Computing? ISSCC 2021: 537-538 - [c14]Victoria Böhm, Christian Wolff, Corinna Geiselhart, Eric Karl, Nina Kleindienst:
Investigating Barriers for the Adoption of the German Contact-Tracing App and the Influence of a Video Intervention on User Acceptance. MuC 2021: 330-337 - 2020
- [c13]Zheng Guo, Jami Wiedemer, Yusung Kim, Prithvee Sundararajan Ramamoorthy, Prateeksha Bindiganavile Sathyaprasad, Smita Shridharan, Daeyeon Kim, Eric Karl:
A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j10]Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl:
A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications. IEEE J. Solid State Circuits 54(1): 210-216 (2019) - 2018
- [c12]Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl:
A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications. ISSCC 2018: 196-198 - 2017
- [j9]Jaydeep P. Kulkarni, John Keane, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang:
5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. IEEE J. Solid State Circuits 52(1): 229-239 (2017) - 2016
- [j8]Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang:
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry. IEEE J. Solid State Circuits 51(1): 222-229 (2016) - [c11]John Keane, Jaydeep Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang:
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. ISSCC 2016: 308-309 - 2015
- [c10]Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Uddalak Bhattacharya, Kevin Zhang:
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology. ISSCC 2015: 1-3 - [c9]Chia-Hong Jan, F. Al-amoody, H.-Y. Chang, T. Chang, Y.-W. Chen, N. Dias, Walid M. Hafez, Doug B. Ingerly, M. Jang, Eric Karl, S. K.-Y. Shi, K. Komeyli, H. Kilambi, A. Kumar, K. Byon, C.-G. Lee, J. Lee, T. Leo, P.-C. Liu, N. Nidhi, R. Olac-vaw, C. Petersburg, K. Phoa, Chetan Prasad, C. Quincy, R. Ramaswamy, T. Rana, L. Rockford, Aravinth Subramaniam, C. Tsai, Peter Vandervoorn, L. Yang, A. Zainuddin, Peng Bai:
A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products. VLSIC 2015: 12- - [c8]Kyung-Hoae Koo, Liqiong Wei, John Keane, Uddalak Bhattacharya, Eric A. Karl, Kevin Zhang:
A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist. VLSIC 2015: 266- - 2013
- [j7]Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Mesut Meterelliyoz, John Keane, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr:
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. IEEE J. Solid State Circuits 48(1): 150-158 (2013) - 2012
- [j6]Prashant Singh, Eric Karl, David T. Blaauw, Dennis Sylvester:
Compact Degradation Sensors for Monitoring NBTI and Oxide Degradation. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1645-1655 (2012) - [c7]Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr:
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. ISSCC 2012: 230-232 - 2011
- [j5]Pramod Kolar, Eric Karl, Uddalak Bhattacharya, Fatih Hamzaoglu, Henry Nho, Yong-Gee Ng, Yih Wang, Kevin Zhang:
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation. IEEE J. Solid State Circuits 46(1): 76-84 (2011) - [j4]Prashant Singh, Eric Karl, Dennis Sylvester, David T. Blaauw:
Dynamic NBTI Management Using a 45 nm Multi-Degradation Sensor. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2026-2037 (2011) - 2010
- [c6]Prashant Singh, Eric Karl, Dennis Sylvester, David T. Blaauw:
Dynamic NBTI management using a 45nm multi-degradation sensor. CICC 2010: 1-4 - [c5]Hyunwoo Nho, Pramod Kolar, Fatih Hamzaoglu, Yih Wang, Eric Karl, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang:
A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation. ISSCC 2010: 346-347
2000 – 2009
- 2009
- [j3]Prashant Singh, Cheng Zhuo, Eric Karl, David T. Blaauw, Dennis Sylvester:
Sensor-Driven Reliability and Wearout Management. IEEE Des. Test Comput. 26(6): 40-49 (2009) - 2008
- [j2]Eric Karl, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge:
Multi-Mechanism Reliability Modeling and Management in Dynamic Systems. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 476-487 (2008) - [c4]Eric Karl, Dennis Sylvester, David T. Blaauw:
Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures. ISQED 2008: 391-395 - [c3]Eric Karl, Prashant Singh, David T. Blaauw, Dennis Sylvester:
Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation. ISSCC 2008: 410-411 - 2006
- [j1]Dennis Sylvester, David T. Blaauw, Eric Karl:
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon. IEEE Des. Test Comput. 23(6): 484-490 (2006) - [c2]Eric Karl, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge:
Reliability modeling and management in dynamic microprocessor-based systems. DAC 2006: 1057-1060 - 2005
- [c1]Eric Karl, Dennis Sylvester, David T. Blaauw:
Timing error correction techniques for voltage-scalable on-chip memories. ISCAS (4) 2005: 3563-3566
Coauthor Index
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