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Hsien-Yuan Liao
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2020 – today
- 2021
- [j2]Chao-Chieh Li, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Yu-Tso Lin, Tsung-Hsien Tsai, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Augusto Ronchini Ximenes, Robert Bogdan Staszewski:
A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 1881-1891 (2021)
2010 – 2019
- 2016
- [c3]Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ronchini Ximenes, Robert Bogdan Staszewski:
A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. VLSI Circuits 2016: 1-2 - 2014
- [c2]Feng-Wei Kuo, Huan-Neng Ron Chen, Kyle Yen, Hsien-Yuan Liao, Chewnpu Jou, Fu-Lung Hsueh, Masoud Babaie, Robert Bogdan Staszewski:
A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS. VLSIC 2014: 1-2
2000 – 2009
- 2009
- [c1]Hsien-Yuan Liao, Jhih-Hong Chen, Hwann-Kaeo Chiou, Shih-Ming Wang:
Harmonic Control Network for 2.6 GHz CMOS Class-F Power Amplifier. ISCAS 2009: 1321-1324 - 2008
- [j1]Hwann-Kaeo Chiou, Hsien-Jui Chen, Hsien-Yuan Liao, Shuw-Guann Lin, Yin-Cheng Chang:
Design formula for band-switching capacitor array in wide tuning range low-phase-noise LC-VCO. Microelectron. J. 39(12): 1687-1692 (2008)
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