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ORCIDKiyoshi Shibayama
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2010 – 2019
- 2018
[j5]Kohei Fujisawa, Atsushi Nunome
, Kiyoshi Shibayama, Hiroaki Hirata:
Design Space Exploration for Implementing a Software-Based Speculative Memory System. Int. J. Softw. Innov. 6(2): 37-49 (2018)- 2017
- [c17]Kohei Fujisawa, Atsushi Nunome, Kiyoshi Shibayama, Hiroaki Hirata:
A software implementation of speculative memory. SNPD 2017: 437-443 - [c16]Sekai Ichii, Shohei Hayashi, Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama:
Performance evaluation of delayed-committing transactional memory. SNPD 2017: 445-451 - [c15]Shingo Shimano, Atsushi Nunome, Yuta Yokoi, Kiyoshi Shibayama, Hiroaki Hirata:
An autonomous configuration scheme of storage tiers for distributed file system. SNPD 2017: 453-458 - 2016
- [c14]Hiroaki Hirata, Atsushi Nunome, Kiyoshi Shibayama:
Speculative memory: An architectural support for explicit speculations in multithreaded programming. ICIS 2016: 1-7 - [c13]Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama:
An interval control method for status propagation in an autonomous distributed storage system. ICIS 2016: 1-6 - 2015
- [j4]Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama:
A Distributed Storage System with Dynamic Tiering for iSCSI Environment. Int. J. Networked Distributed Comput. 3(1): 42-50 (2015) - [c12]Shingo Shimano, Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama:
An Information Propagation Scheme for an Autonomous Distributed Storage System in iSCSI Environment. ACIT-CSI 2015: 142-147 - [c11]Sekai Ichii, Saki Tashiro, Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama:
Hardware Transactional Memory with Delayed-Committing. ACIT-CSI 2015: 154-161 - [c10]Yuki Shoji, Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama:
A Large-Scale Speculation for the Thread-Level Parallelization. ACIT-CSI 2015: 162-168 - 2014
- [c9]Sekai Ichii, Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama:
A Lazy-Updating Snoop Cache Protocol for Transactional Memory. IIAI-AAI 2014: 636-643 - [c8]Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama:
A Distributed Storage System with Dynamic Tiering for iSCSI Environment. IIAI-AAI 2014: 644-649 - 2010
- [c7]Atsushi Nunome, Hiroaki Hirata, Masayuki Fukuzawa, Kiyoshi Shibayama:
Development of an e-learning back-end system for code assessment in elementary programming practice. SIGUCCS 2010: 181-186
2000 – 2009
- 2004
- [j3]Atsushi Nunome, Hiroaki Hirata, Haruo Niimi, Kiyoshi Shibayama:
Performance evaluation of dynamic load balancing scheme with load prediction mechanism using the load growing acceleration for massively parallel computers. Syst. Comput. Jpn. 35(11): 69-79 (2004) - 2002
- [j2]Shuji Yamamura, Tadafumi Kadota, Hiroaki Hirata, Haruo Niimi, Kiyoshi Shibayama:
Evaluation of a data preload mechanism for a linked list structure. Syst. Comput. Jpn. 33(3): 21-30 (2002)
1980 – 1989
- 1987
- [c6]Kiyoshi Shibayama, Masaaki Yamamoto, Hiroaki Hirata, Yasushi Konoh, Takanori Sanetoh, Hiroshi Hagiwara:
KPR: A Logic Programming Language-Oriented Parallel Machine. LP 1987: 113-131 - 1986
- [c5]Shinji Tomita, Kiyoshi Shibayama, Toshiyuki Nakata, Shinji Yuasa, Hiroshi Hagiwara:
A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp Machines. ISCA 1986: 280-289 - 1983
- [c4]Shinji Tomita, Kiyoshi Shibayama, Toshiaki Kitamura, Toshiyuki Nakata, Hiroshi Hagiwara:
A User-Microprogrammable, Local Host Computer With Low-Level Parallelism. ISCA 1983: 151-157 - 1980
- [j1]Hiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama:
A Dynamically Microprogammable Computer with Low-Level Parallelism. IEEE Trans. Computers 29(7): 577-595 (1980) - [c3]Kiyoshi Shibayama, Shinji Tomita, Hiroshi Hagiwara, Katsuhiro Yamazaki, Toshiaki Kitamura:
Performance Evaluation and Improvement of a Dynamically Microprogrammable Computer with Low-Level Parallelism. IFIP Congress 1980: 181-186 - [c2]Shinji Tomita, Kiyoshi Shibayama, Toshiaki Kitamura, Hiroshi Hagiwara:
Performance evaluation and improvement of a dynamically microprogrammable computer with low-level parallelism. MICRO 1980: 79-89
1970 – 1979
- 1977
- [c1]Shinji Tomita, Kiyoshi Shibayama, Shigeru Oyanagi, Hiroshi Hagiwara:
Hardware Organization of a Low Level Parallel Processor. IFIP Congress 1977: 855-860
Coauthor Index
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