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2020 – today
- 2022
[j7]John M. Emmert
, Anvesh Perumalla, Tristan J. Hudson, Luis Concha:
THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2906-2915 (2022)- 2021
- [c19]John M. Emmert, Sara A. VanDewerker:
EMC: Efficient Muller C-Element Implementation for High Bit-width Asynchronous Applications. MWSCAS 2021: 816-819 - [c18]Aaron Ruen, Abhijeet Barua, Rashmi Jha, John M. Emmert:
Fully BEOL-Compatible Switch Boxes Using RRAMs and Thin Film Transistors for Reconfigurable and Secure ICs. MWSCAS 2021: 820-825 - [c17]Carla Purdy, John M. Emmert, Rashmi Jha, Ranga Vemuri:
Educating the Next Generation of Cybersecurity Defenders at the University of Cincinnati. MWSCAS 2021: 836-839 - 2020
- [c16]John M. Emmert, Anvesh Perumalla, Luis Concha:
An Asynchronous FPGA THx2 Programmable Cell for Mitigating Side-Channel Attacks. MWSCAS 2020: 840-843
2000 – 2009
- 2007
- [j6]John M. Emmert, Charles E. Stroud, Miron Abramovici:
Online Fault Tolerance for FPGA Logic Blocks. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 216-226 (2007) - 2006
- [j5]Jason A. Cheatham, John M. Emmert, Stanley Baumgart:
A survey of fault tolerant methodologies for FPGAs. ACM Trans. Design Autom. Electr. Syst. 11(2): 501-533 (2006) - 2004
- [j4]Miron Abramovici, Charles E. Stroud, John M. Emmert:
Online BIST and BIST-based diagnosis of FPGA logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1284-1294 (2004) - 2003
- [j3]John M. Emmert, Sandeep Lodha, Dinesh Bhatia:
On Using Tabu Search for Design Automation of VLSI Systems. J. Heuristics 9(1): 75-90 (2003) - [c15]John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani:
A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits. DFT 2003: 303- - [c14]John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani:
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals. DFT 2003: 361-368 - 2001
- [j2]John M. Emmert, Dinesh K. Bhatia:
Two-dimensional Placement Using Tabu Search. VLSI Design 12(1): 13-23 (2001) - [c13]John M. Emmert, Jason A. Cheatham:
On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router . DFT 2001: 149- - [c12]John M. Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici:
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. DFT 2001: 445-454 - [c11]Miron Abramovici, John M. Emmert, Charles E. Stroud:
Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems. Evolvable Hardware 2001: 73-92 - [c10]Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John M. Emmert:
On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. IOLTW 2001: 27-33 - 2000
- [j1]John M. Emmert, Dinesh K. Bhatia:
A Fault Tolerant Technique for FPGAs. J. Electron. Test. 16(6): 591-606 (2000) - [c9]John M. Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici:
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. FCCM 2000: 165-174 - [c8]John M. Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici:
Performance Penalty for Fault Tolerance in Roving STARs. FPL 2000: 545-554 - [c7]Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John M. Emmert:
Improving On-Line BIST-Based Diagnosis for Roving STARs. IOLTW 2000: 31-39 - [c6]Charles E. Stroud, John M. Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic:
Bridging fault extraction from physical design data for manufacturing test development. ITC 2000: 760-769
1990 – 1999
- 1999
- [c5]John M. Emmert, Dinesh Bhatia:
A Methodology for Fast FPGA Floorplanning. FPGA 1999: 47-56 - [c4]John M. Emmert, Dinesh Bhatia:
Tabu Search: Ultra-Fast Placement for FPGAs. FPL 1999: 81-90 - [c3]John M. Emmert, Dinesh Bhatia:
Fast timing driven placement using tabu search. ISCAS (1) 1999: 302-305 - 1998
- [c2]John M. Emmert, Akash Randhar, Dinesh Bhatia:
Fast Floorplanning for FPGAs. FPL 1998: 129-138 - 1997
- [c1]John M. Emmert, Dinesh Bhatia:
Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. FPL 1997: 141-150
Coauthor Index
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