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2020 – today
- 2024
[c10]Siddharth Saxena, Sudhir S. Kudva, Vijay Srinivasan, Miguel Rodriguez, Walter Li, Shalimar Rasheed, Gaurav Ajwani, Tezaswi Raja, Santosh A, C. Thomas Gray:
A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode. CICC 2024: 1-2
2010 – 2019
- 2019
- [c9]Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany:
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. ASYNC 2019: 27-35 - 2015
- [j3]Ignatius Bezzam, Chakravarthy Mathiazhagan, Tezaswi Raja, Shoba Krishnan:
An Energy-Recovering Reconfigurable Series Resonant Clocking Scheme for Wide Frequency Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1766-1775 (2015) - 2013
- [c8]Ignatius Bezzam, Shoba Krishnan, Tezaswi Raja, Chakravarthy Mathiazhagan:
Low power low voltage wide frequency resonant clock and data circuits for power reductions. LASCAS 2013: 1-4 - 2010
- [c7]Tezaswi Raja, Samiha Mourad:
Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial. DELTA 2010: 303-309
2000 – 2009
- 2009
- [j2]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Variable Input Delay CMOS Logic for Low Power Design. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1534-1545 (2009) - 2006
- [j1]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Transistor Sizing of Logic Gates to Maximize Input Delay Variability. J. Low Power Electron. 2(1): 121-128 (2006) - 2005
- [c6]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Design of Variable Input Delay Gates for Low Dynamic Power Circuits. PATMOS 2005: 436-445 - [c5]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Variable Input Delay CMOS Logic for Low Power Design. VLSI Design 2005: 598-605 - 2004
- [c4]Tezaswi Raja, Manish Parashar:
Using a Jini based desktop Grid for test vector compaction and a refined economic model. CCGRID 2004: 798-805 - [c3]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
A Tuturial on the Emerging Nanotechnology Devices. VLSI Design 2004: 343-360 - [c2]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. VLSI Design 2004: 1035-1040 - 2003
- [c1]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. VLSI Design 2003: 527-532
Coauthor Index
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