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2020 – today
- 2022
[c52]Francesco Bruschi, Tommaso Paulon, Vincenzo Rana, Donatella Sciuto:
A Protocol for On-Chain Tenders. PerCom Workshops 2022: 273-278- 2021
- [j9]Francesco Bruschi
, Vincenzo Rana, Alessio Pagani, Donatella Sciuto:
Tunneling Trust Into the Blockchain: A Merkle Based Proof System for Structured Documents. IEEE Access 9: 103758-103771 (2021) - [c51]Francesco Bruschi, Tommaso Paulon, Vincenzo Rana, Donatella Sciuto:
A privacy preserving identification protocol for smart contracts. ISCC 2021: 1-6 - 2020
- [c50]Francesco Bruschi, Manuel Tumiati, Vincenzo Rana, Mattia Bianchi, Donatella Sciuto:
A Decentralized System for Fair Token Distribution and Seamless Users Onboarding. ISCC 2020: 1-6 - [c49]Francesco Bruschi, Vincenzo Rana, Alessio Pagani, Donatella Sciuto:
Acknowledging Value of Personal Information: a Privacy Aware Data Market for Health and Social Research. DLT@ITASEC 2020
2010 – 2019
- 2018
- [j8]Francesco Bruschi, Vincenzo Rana, Lorenzo Gentile, Donatella Sciuto:
Mine with it or sell it: the superhashing power dilemma. SIGMETRICS Perform. Evaluation Rev. 46(3): 127-130 (2018) - [j7]Alessandro Antonio Nacci, Vincenzo Rana, Bharathan Balaji, Paola Spoletini, Rajesh K. Gupta, Donatella Sciuto, Yuvraj Agarwal:
BuildingRules: A Trigger-Action-Based System to Manage Complex Commercial Buildings. ACM Trans. Cyber Phys. Syst. 2(2): 13:1-13:22 (2018) - 2017
- [c48]Pierandrea Cancian, Guido Walter Di Donato, Vincenzo Rana, Marco D. Santambrogio:
An embedded Gabor-based palm vein recognition system. BHI 2017: 405-408 - [c47]Alessio Pagani, Francesco Bruschi, Vincenzo Rana:
Time of arrival cumulative probability in public transportation travel assistance. ITSC 2017: 1-6 - [c46]Alessio Pagani, Francesco Bruschi, Vincenzo Rana, Marcello Restelli:
User context estimation for public travel assistance and intelligent service scheduling. ITSC 2017: 1-8 - 2016
- [j6]Vincenzo Rana, Ivan Beretta, Francesco Bruschi, Alessandro Antonio Nacci, David Atienza, Donatella Sciuto:
Efficient Hardware Design of Iterative Stencil Loops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2018-2031 (2016) - [j5]Ivan Beretta, Vincenzo Rana, Abdulkadir Akin, Alessandro Antonio Nacci, Donatella Sciuto, David Atienza:
Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices. ACM Trans. Embed. Comput. Syst. 15(3): 44:1-44:27 (2016) - [c45]Andrea Piscitello, Alessandro Antonio Nacci, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
Ruleset Minimization in Multi-tenant Smart Buildings. CSE/EUC/DCABES 2016: 72-79 - [c44]Alessio Pagani, Francesco Bruschi, Vincenzo Rana, Marcello Restelli:
Reconstruction of public transport state. ITSC 2016: 2285-2292 - [c43]Andrea Piscitello, Alessandro Antonio Nacci, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
Sink state analysis in multi-tenant smart buildings. RTSI 2016: 1-4 - 2014
- [j4]Juan Antonio Clemente, Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto:
A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms. ACM Trans. Reconfigurable Technol. Syst. 7(2): 9:1-9:27 (2014) - [c42]Alessandro Antonio Nacci, Vincenzo Rana, Donatella Sciuto:
A Perspective Vision on Complex Residential Building Management Systems. EUC 2014: 209-214 - [c41]Vincenzo Rana, Francesco Bruschi, Marco Paolieri, Donatella Sciuto, Marco Domenico Santambrogio:
On How to Efficiently Implement Regular Expression Matching on FPGA-Based Systems. EUC 2014: 304-309 - [c40]Alessandro Antonio Nacci, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
Improving the security and the scalability of the AES algorithm (abstract only). FPGA 2014: 256 - [c39]Alessandro Antonio Nacci, Vincenzo Rana, Donatella Sciuto, Marco Domenico Santambrogio:
An Open-Source, Efficient, and Parameterizable Hardware Implementation of the AES Algorithm. ISPA 2014: 85-92 - [c38]Giorgio Conte, Massimo De Marchi, Alessandro Antonio Nacci, Vincenzo Rana, Donatella Sciuto:
BlueSentinel: a first approach using iBeacon for an energy efficient occupancy detection system. BuildSys@SenSys 2014: 11-19 - [c37]A. A. Nacci, Giovanni Bettinazzi, Christian Pilato, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces. WF-IoT 2014: 485-490 - 2013
- [j3]Vincenzo Rana, Alessandro Antonio Nacci, Ivan Beretta, Marco D. Santambrogio, David Atienza, Donatella Sciuto:
Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms. IEEE Des. Test 30(4): 71-80 (2013) - [c36]Alessandro Antonio Nacci, Vincenzo Rana, Francesco Bruschi, Donatella Sciuto, Ivan Beretta, David Atienza:
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices. DAC 2013: 52:1-52:6 - 2012
- [c35]Paolo Roberto Grassi, Vincenzo Rana, Ivan Beretta, Donatella Sciuto:
B2IRS: A Technique to Reduce BAN-BAN Interferences in Wireless Sensor Networks. BSN 2012: 46-51 - [c34]Paolo Roberto Grassi, Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto:
Knowledge-based design space exploration of wireless sensor networks. CODES+ISSS 2012: 225-234 - [c33]Ivan Beretta, Francisco J. Rincón, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana, David Atienza:
Design exploration of energy-performance trade-offs for wireless sensor networks. DAC 2012: 1043-1048 - [c32]Paolo Roberto Grassi, Vincenzo Rana, Ivan Beretta, Donatella Sciuto:
Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor Networks. DSD 2012: 874-881 - [c31]Ivan Beretta, Francisco J. Rincón, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana, David Atienza, Donatella Sciuto:
Model-based design for wireless body sensor network nodes. LATW 2012: 1-6 - 2011
- [j2]Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto:
Island-Based Adaptable Embedded System Design. IEEE Embed. Syst. Lett. 3(2): 53-57 (2011) - [j1]Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto:
A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1211-1224 (2011) - [c30]Francesco Bruschi, Francesco Perini, Vincenzo Rana, Donatella Sciuto:
An efficient Quantum-Dot Cellular Automata adder. DATE 2011: 1220-1223 - [c29]Abdulkadir Akin, Ivan Beretta, A. A. Nacci, Vincenzo Rana, Marco D. Santambrogio, David Atienza:
A high-performance parallel implementation of the Chambolle algorithm. DATE 2011: 1436-1441 - [c28]Juan Antonio Clemente, Vincenzo Rana, Donatella Sciuto, Ivan Beretta, David Atienza:
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware. FPL 2011: 177-180 - [c27]Francesco Bruschi, Antonio Miele, Vincenzo Rana:
On-chip network resource management design and validation. ICSAMOS 2011: 249-254 - 2010
- [c26]Marco D. Santambrogio, Vincenzo Rana, Ivan Beretta, Donatella Sciuto:
Operating system runtime management of partially dynamically reconfigurable embedded systems. ESTIMedia 2010: 1-10 - [c25]Francesco Bruschi, Marco Paolieri, Vincenzo Rana:
A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching. FPL 2010: 44-49 - [c24]Vincenzo Rana, Donatella Sciuto:
A novel design framework for the design of reconfigurable systems based on NoCs. ACM Great Lakes Symposium on VLSI 2010: 1-2 - [c23]Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto:
Run-time mapping of applications on FPGA-based reconfigurable systems. ISCAS 2010: 3329-3332
2000 – 2009
- 2009
- [c22]Vincenzo Rana, Srinivasan Murali, David Atienza, Marco D. Santambrogio, Luca Benini, Donatella Sciuto:
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. CODES+ISSS 2009: 325-334 - [c21]Dario Cozzi, Claudia Farè, Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices. ACM Great Lakes Symposium on VLSI 2009: 421-424 - [c20]Ivan Beretta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
On-line task management for a reconfigurable cryptographic architecture. IPDPS 2009: 1-4 - 2008
- [c19]Carlo Curino, Luca Fossati, Vincenzo Rana, Francesco Redaelli, Marco D. Santambrogio, Donatella Sciuto:
The Shining embedded system design methodology based on self dynamic reconfigurable architectures. ASP-DAC 2008: 595-600 - [c18]Andrea Cuoccio, Paolo Roberto Grassi, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
A Generation Flow for Self-Reconfiguration Controllers Customization. DELTA 2008: 279-284 - [c17]Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow. DELTA 2008: 405-409 - [c16]Vincenzo Rana, Matteo Matteucci, Daniele Caltabiano, Roberto Sannino, Andrea Bonarini:
Low cost smartcams design. ESTIMedia 2008: 27-32 - [c15]Francesco Bruschi, Vincenzo Rana, Donatella Sciuto:
An architecture for dynamically reconfigurable real time audio processing systems. ESTIMedia 2008: 81-86 - [c14]Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Francesco Bruschi:
A Requirements-Driven Simulation Framework for Communication Infrastructures Design. FDL 2008: 111-117 - [c13]Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Francesco Bruschi:
Design of Communication Infrastructures for Reconfigurable Systems. FDL (Selected Papers) 2008: 291-307 - [c12]Marco D. Santambrogio, Vincenzo Rana, Donatella Sciuto:
Operating system support for online partial dynamic reconfiguration management. FPL 2008: 455-458 - [c11]Alessio Montone, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures. IPDPS 2008: 1-8 - [c10]Simone Corbetta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
A light-weight Network-on-Chip architecture for dynamically reconfigurable systems. ICSAMOS 2008: 49-56 - [c9]Vincenzo Rana, David Atienza, Marco D. Santambrogio, Donatella Sciuto, Giovanni De Micheli:
A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication. VLSI-SoC (Selected Papers) 2008: 232-250 - 2007
- [c8]Marco D. Santambrogio, Seda Ogrenci Memik, Vincenzo Rana, Umut A. Acar, Donatella Sciuto:
A novel SoC design methodology combining adaptive software and reconfigurable hardware. ICCAD 2007: 303-308 - [c7]Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Boris Kettelhoit, Markus Köster, Mario Porrmann, Ulrich Rückert:
Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. IPDPS 2007: 1-8 - [c6]Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
Dynamic Reconfigurability in Embedded System Design. ISCAS 2007: 2734-2737 - [c5]Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto:
An adaptive genetic algorithm for dynamically reconfigurable modules allocation. VLSI-SoC (Selected Papers) 2007: 1-18 - [c4]Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto:
An adaptive genetic algorithm for dynamically reconfigurable modules allocation. VLSI-SoC 2007: 128-133 - 2006
- [c3]Vincenzo Rana, Marco D. Santambrogio, Seda Ogrenci Memik, Donatella Sciuto:
Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology. FPT 2006: 293-296 - [c2]Fabrizio Ferrandi, Giovanna Ferrara, Roberto Palazzo, Vincenzo Rana, Marco D. Santambrogio:
VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow. IPDPS 2006 - [c1]Matteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow. VLSI-SoC 2006: 74-79
Coauthor Index
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