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ORCIDA. De Keersgieter
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2010 – 2019
- 2017
[c6]Romain Ritzenthaler, Hans Mertens, A. De Keersgieter, Jérôme Mitard, Dan Mocuta, N. Horiguchi:
Isolation of nanowires made on bulk wafers by ground plane doping. ESSDERC 2017: 300-303- 2016
- [c5]Thomas Chiarella, S. Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, A. De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean:
Towards high performance sub-10nm finW bulk FinFET technology. ESSDERC 2016: 131-134 - 2015
- [c4]Geert Eneman, A. De Keersgieter, Anda Mocuta, Nadine Collaert, Aaron Thean:
FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below. ICICDT 2015: 1-4 - [c3]Ben Kaczer, Jacopo Franco, M. Cho, Tibor Grasser
, Philippe J. Roussel, Stanislav Tyaginov, M. Bina, Yannick Wimmer, Luis-Miguel Procel, Lionel Trojman, Felice Crupi, Gregory Pitner, V. Putcha, Pieter Weckx, Erik Bury, Z. Ji, A. De Keersgieter, Thomas Chiarella, Naoto Horiguchi, Guido Groeseneken, Aaron Thean:
Origins and implications of increased channel hot carrier variability in nFinFETs. IRPS 2015: 3 - 2013
- [c2]Doyoung Jang, Marie Garcia Bardon, Dmitry Yakimets, Kenichi Miyaguchi, A. De Keersgieter, Thomas Chiarella, Romain Ritzenthaler, Morin Dehan, Abdelkarim Mercha:
STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process. ESSDERC 2013: 159-162
2000 – 2009
- 2009
- [c1]Thomas Chiarella, Liesbeth Witters, Abdelkarim Mercha, Christoph Kerner, Rok Dittrich, Michal Rakowski, Claude Ortolland, Lars-Åke Ragnarsson, Bertrand Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, R. Rooyackers, C. Vrancken, S. Brus, A. Lauwers, Philippe Absil, S. Biesemans, Thomas Y. Hoffmann:
Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? ESSCIRC 2009: 84-87 - 2002
- [j1]Ben Kaczer, Robin Degraeve, Mahmoud Rasras, A. De Keersgieter, K. Van de Mieroop, Guido Groeseneken:
Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study. Microelectron. Reliab. 42(4-5): 555-564 (2002)
Coauthor Index
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