
BibTeX records: Robert Yung
@article{DBLP:journals/csur/Yung96, author = {Robert Yung}, title = {The Importance of Process Technology to Architecture}, journal = {{ACM} Comput. Surv.}, volume = {28}, number = {4es}, pages = {37}, year = {1996}, url = {https://doi.org/10.1145/242224.242270}, doi = {10.1145/242224.242270}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/csur/Yung96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/Yung96, author = {Robert Yung}, editor = {Stephen W. Melvin and Steve Beaty}, title = {Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture}, booktitle = {Proceedings of the 29th Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 29, Paris, France, December 2-4, 1996}, pages = {178--190}, publisher = {{ACM/IEEE} Computer Society}, year = {1996}, url = {https://doi.org/10.1109/MICRO.1996.566460}, doi = {10.1109/MICRO.1996.566460}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/micro/Yung96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/compcon/GreenleyBCCEFFGGGHKKKLMMNNPPPTWYYYYZ95, author = {Dale Greenley and J. Bauman and D. Chang and Dennis Chen and R. Eltejaein and P. Ferolito and P. Fu and Robert B. Garner and D. Greenhill and H. Grewal and Kalon Holdbrook and B. Kim and Leslie Kohn and H. Kwan and M. Levitt and Guillermo Maturana and D. Mrazek and Chitresh Narasimhaiah and Kevin Normoyle and N. Parveen and P. Patel and A. Prabhu and Marc Tremblay and Michelle Wong and L. Yang and Krishna Yarlagadda and Robert K. Yu and Robert Yung and Gregory B. Zyner}, title = {UltraSPARC: The Next Generation Superscalar 64-bit {SPARC}}, booktitle = {{COMPCON} '95: Technologies for the Information Superhighway, Digest of Papers, San Francisco, California, USA, March 5-9, 1995}, pages = {442--451}, publisher = {{IEEE} Computer Society}, year = {1995}, url = {https://doi.org/10.1109/CMPCON.1995.512421}, doi = {10.1109/CMPCON.1995.512421}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/compcon/GreenleyBCCEFFGGGHKKKLMMNNPPPTWYYYYZ95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/YungW95, author = {Robert Yung and Neil C. Wilhelm}, title = {Caching processor general registers}, booktitle = {1995 International Conference on Computer Design {(ICCD} '95), {VLSI} in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings}, pages = {307--312}, publisher = {{IEEE} Computer Society}, year = {1995}, url = {https://doi.org/10.1109/ICCD.1995.528826}, doi = {10.1109/ICCD.1995.528826}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/iccd/YungW95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/amai/DespainY91, author = {Alvin M. Despain and Robert Yung}, title = {An integrated prolog architecture for symbolic and numeric executions}, journal = {Ann. Math. Artif. Intell.}, volume = {4}, pages = {107--133}, year = {1991}, url = {https://doi.org/10.1007/BF01531175}, doi = {10.1007/BF01531175}, timestamp = {Sun, 28 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/amai/DespainY91.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }

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