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ORCIDRakesh Kumar 0003
Person information
- affiliation: Norwegian University of Science and Technology (NTNU), Trondheim, Norway
- affiliation (former): University of Edinburgh, UK
- not to be confused with: Rakesh Kumar 0002
Other persons with the same name
- Rakesh Kumar — disambiguation page
- Rakesh Kumar 0001 (aka: Rakesh "Teddy" Kumar) — SRI International, Center for Vision Technologies, Princeton, NJ, USA
- Rakesh Kumar 0002
![[0009-0008-1535-1889]](https://dblp.org/img/orcid-mark.12x12.png "0009-0008-1535-1889")
— University of Illinois at Urbana-Champaign, IL, USA (and 1 more) - Rakesh Kumar 0004 — Indraprastha University, University School of Information, Communication and Technology, New Delhi, India
- Rakesh Kumar 0005 — Massachusetts Institute of Technology, Cambridge, USA
- Rakesh Kumar 0006 — Tata Institute of Fundamental Research, Centre For Applicable Mathematics, Bangalore, India (and 1 more)
- Rakesh Kumar 0007 — Microsoft Corp, Redmond, Washington, USA (and 1 more)
- Rakesh Kumar 0008 — Madan Mohan Malaviya University of Technology, Gorakhpur, India
- Rakesh Kumar 0009 — Chandigarh University, Mohali, Punjab, India
- Rakesh Kumar 0010 — Indian Institute of Technology, Banaras Hindu University, Varanasi, India
- Rakesh Kumar 0011 — Central University of Haryana, Haryana, India (and 1 more)
- Rakesh Kumar 0012 — Indian Institute of Information Technology, Allahabad, UP, India
- Rakesh Kumar 0013 — Maharishi Markandeshwar University, Mullana, India
- Rakesh Kumar 0014 — Polytechnic University, Brooklyn, NY, USA
- Rakesh Kumar 0015 — Shri Mata Vaishno Devi University, School of Mathematics, India
- Rakesh Kumar 0016 — University of Illinois Urbana-Champaign, Department of Electrical and Computer Engineering, USA
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2020 – today
- 2024
[c21]Truls Asheim, Magnus Jahre, Rakesh Kumar:
CoFaaS: Automatic Transformation-based Consolidation of Serverless Functions. SESAME@EuroSys 2024: 1-8- 2023
- [c20]Truls Asheim, Boris Grot, Rakesh Kumar:
A Storage-Effective BTB Organization for Servers. HPCA 2023: 1153-1167 - [c19]Konstantinos Kanellopoulos, Hong Chul Nam, Nisa Bostanci, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Davide Basilio Bartolini, Onur Mutlu:
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources. MICRO 2023: 1178-1195 - [c18]Konstantinos Kanellopoulos, Rahul Bera, Kosta Stojiljkovic, F. Nisa Bostanci, Can Firtina, Rachata Ausavarungnirun, Rakesh Kumar, Nastaran Hajinazar, Mohammad Sadrosadati, Nandita Vijaykumar, Onur Mutlu:
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings. MICRO 2023: 1196-1212 - [i5]Truls Asheim, Boris Grot, Rakesh Kumar:
A Storage-Effective BTB Organization for Servers. CoRR abs/2301.03899 (2023) - [i4]Konstantinos Kanellopoulos, Hong Chul Nam, F. Nisa Bostanci, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Davide Basilio Bartolini, Onur Mutlu:
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources. CoRR abs/2310.04158 (2023) - 2022
- [j5]Rakesh Kumar, Mehdi Alipour, David Black-Schaffer:
Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores. ACM Trans. Archit. Code Optim. 19(2): 25:1-25:28 (2022) - [c17]Truls Asheim, Boris Grot, Rakesh Kumar:
A Specialized BTB Organization for Servers. PACT 2022: 548-549 - [c16]Odin Ugedal, Rakesh Kumar:
Mitigating Unnecessary Throttling in Linux CFS Bandwidth Control. SBAC-PAD 2022: 336-345 - [c15]Truls Asheim, Tanvir Ahmed Khan, Baris Kasikci, Rakesh Kumar:
Impact of microarchitectural state reuse on serverless functions. WOSC@Middleware 2022: 7-12 - [i3]Rakesh Kumar, Mehdi Alipour, David Black-Schaffer:
Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores. CoRR abs/2201.00485 (2022) - 2021
- [j4]Truls Asheim, Boris Grot, Rakesh Kumar:
BTB-X: A Storage-Effective BTB Organization. IEEE Comput. Archit. Lett. 20(2): 134-137 (2021) - [c14]Tanvir Ahmed Khan, Nathan Brown, Akshitha Sriraman, Niranjan K. Soundararajan, Rakesh Kumar, Joseph Devietti, Sreenivas Subramoney, Gilles A. Pokam, Heiner Litz, Baris Kasikci:
Twig: Profile-Guided BTB Prefetching for Data Center Applications. MICRO 2021: 816-829 - [i2]Rakesh Kumar, Alejandro Martínez, Antonio Gonzalez:
A Variable Vector Length SIMD Architecture for HW/SW Co-designed Processors. CoRR abs/2102.13410 (2021) - 2020
- [j3]Rakesh Kumar, Boris Grot:
Shooting Down the Server Front-End Bottleneck. ACM Trans. Comput. Syst. 38(3-4): 7:1-7:30 (2020) - [c13]Mehdi Alipour, Stefanos Kaxiras, David Black-Schaffer, Rakesh Kumar:
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors. HPCA 2020: 424-434 - [c12]Fredrik Strupe, Rakesh Kumar:
Uncovering Hidden Instructions in Armv8-A Implementations. HASP@MICRO 2020: 3:1-3:9 - [i1]Truls Asheim, Rakesh Kumar, Boris Grot:
Fetch-Directed Instruction Prefetching Revisited. CoRR abs/2006.13547 (2020)
2010 – 2019
- 2019
- [c11]Mehdi Alipour, Rakesh Kumar, Stefanos Kaxiras, David Black-Schaffer:
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors. DATE 2019: 716-721 - [c10]Rakesh Kumar, Mehdi Alipour, David Black-Schaffer:
Freeway: Maximizing MLP for Slice-Out-of-Order Execution. HPCA 2019: 558-569 - 2018
- [c9]Rakesh Kumar, Boris Grot, Vijay Nagarajan:
Blasting through the Front-End Bottleneck with Shotgun. ASPLOS 2018: 30-42 - 2017
- [c8]Rakesh Kumar, Cheng-Chieh Huang, Boris Grot, Vijay Nagarajan:
Boomerang: A Metadata-Free Architecture for Control Flow Delivery. HPCA 2017: 493-504 - [c7]Rakesh Kumar, José Cano, Aleksandar Brankovic, Demos Pavlou, Kyriakos Stavrou, Enric Gibert, Alejandro Martínez, Antonio Gonzalez:
HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation. ISPASS 2017: 185-194 - 2016
- [j2]Rakesh Kumar, Alejandro Martínez, Antonio González:
Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment. ACM Trans. Comput. Syst. 33(4): 12:1-12:33 (2016) - [c6]José Cano, Rakesh Kumar, Aleksandar Brankovic, Demos Pavlou, Kyriakos Stavrou, Enric Gibert, Alejandro Martínez, Antonio González:
Quantitative characterization of the software layer of a HW/SW co-designed processor. IISWC 2016: 138-147 - [c5]Cheng-Chieh Huang, Rakesh Kumar, Marco Elver, Boris Grot, Vijay Nagarajan:
C3D: Mitigating the NUMA bottleneck via coherent DRAM caches. MICRO 2016: 36:1-36:12 - 2014
- [j1]Rakesh Kumar, Alejandro Martínez, Antonio González:
Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment. ACM Trans. Archit. Code Optim. 11(3): 25:1-25:23 (2014) - 2013
- [c4]Rakesh Kumar, Alejandro Martínez, Antonio González:
Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment. HiPC 2013: 79-88 - [c3]Rakesh Kumar, Alejandro Martínez, Antonio González:
Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment. HPCC/EUC 2013: 518-525 - [c2]Rakesh Kumar, Alejandro Martínez, Antonio González:
Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment. SBAC-PAD 2013: 81-88 - 2012
- [c1]Rakesh Kumar, Alejandro Martínez, Antonio González:
Speculative dynamic vectorization for HW/SW co-designed processors. PACT 2012: 459-460
Coauthor Index
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