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Chung-Kuan Cheng
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- affiliation: University of California, San Diego, USA
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2020 – today
- 2024
- [i12]Chester Holtz, Yucheng Wang, Chung-Kuan Cheng, Bill Lin:
On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations. CoRR abs/2403.00103 (2024) - 2023
- [j94]Chung-Kuan Cheng, Chester Holtz, Andrew B. Kahng, Bill Lin, Uday Mallappa:
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs. ACM Trans. Design Autom. Electr. Syst. 28(4): 52:1-52:31 (2023) - [c205]Pengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang:
Placement Initialization via Sequential Subspace Optimization with Sphere Constraints. ISPD 2023: 133-140 - [c204]Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang:
Assessment of Reinforcement Learning for Macro Placement. ISPD 2023: 158-166 - [c203]Chung-Kuan Cheng, Andrew B. Kahng, Bill Lin, Yucheng Wang, Dooseok Yoon:
Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration. SLIP 2023: 2:1-2:10 - [c202]Chung-Kuan Cheng, Bill Lin, Byeonggon Kang, Yucheng Wang:
Invited Paper: The Scope and Challenges of Scaling in Advanced Technologies. SLIP 2023: 6:1-6:8 - [i11]Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang:
Assessment of Reinforcement Learning for Macro Placement. CoRR abs/2302.11014 (2023) - [i10]Kuan-Jung Chiang, Steven Dong, Chung-Kuan Cheng, Tzyy-Ping Jung:
Using EEG Signals to Assess Workload during Memory Retrieval in a Real-world Scenario. CoRR abs/2305.08044 (2023) - [i9]Chester Holtz, Pengwen Chen, Alexander Cloninger, Chung-Kuan Cheng, Gal Mishne:
Semi-Supervised Laplacian Learning on Stiefel Manifolds. CoRR abs/2308.00142 (2023) - 2022
- [j93]Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin:
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform. IEEE Access 10: 65971-65981 (2022) - [j92]Uday Mallappa, Chung-Kuan Cheng, Bill Lin:
JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation. IEEE Des. Test 39(6): 16-27 (2022) - [j91]Uday Mallappa, Chung-Kuan Cheng, Bill Lin:
Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation. IEEE Embed. Syst. Lett. 14(4): 175-178 (2022) - [j90]Daeyeal Lee, Bill Lin, Chung-Kuan Cheng:
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing. ACM Trans. Archit. Code Optim. 19(1): 5:1-5:21 (2022) - [j89]Chung-Kuan Cheng, Andrew B. Kahng, Hayoung Kim, Minsoo Kim, Daeyeal Lee, Dongwon Park, Mingyu Woo:
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1495-1508 (2022) - [j88]Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Daeyeal Lee, Bill Lin:
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. 30(8): 1059-1072 (2022) - [c201]Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz:
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. ASP-DAC 2022: 288-293 - [c200]Pengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang:
Placement initialization via a projected eigenvector algorithm: late breaking results. DAC 2022: 1398-1399 - [i8]Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz:
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. CoRR abs/2210.14259 (2022) - 2021
- [j87]Daeyeal Lee, Bill Lin, Chung-Kuan Cheng:
SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC. IEEE Embed. Syst. Lett. 13(4): 158-161 (2021) - [j86]Pengwen Chen, Chung-Kuan Cheng, Xinyuan Wang:
Arnoldi Algorithms with Structured Orthogonalization. SIAM J. Numer. Anal. 59(1): 370-400 (2021) - [j85]He-Teng Zhang, Masahiro Fujita, Chung-Kuan Cheng, Jie-Hong R. Jiang:
SAT-Based On-Track Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 735-747 (2021) - [j84]Daeyeal Lee, Dongwon Park, Chia-Tung Ho, Ilgweon Kang, Hayoung Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng:
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2142-2155 (2021) - [j83]Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin, Dongwon Park:
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1178-1191 (2021) - [c199]Ting-Chou Lin, Devon J. Merrill, Yen-Yi Wu, Chester Holtz, Chung-Kuan Cheng:
A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs. ASP-DAC 2021: 170-175 - [c198]Uday Mallappa, Chung-Kuan Cheng:
GRA-LPO: Graph Convolution Based Leakage Power Optimization. ASP-DAC 2021: 697-702 - [c197]Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Minsoo Kim, Daeyeal Lee, Bill Lin, Dongwon Park, Mingyu Woo:
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation. ICCD 2021: 366-373 - [c196]Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Bill Lin:
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning. SLIP 2021: 8-15 - 2020
- [j82]Eric Chang, Chung-Kuan Cheng, Anushka Gupta, Po-Ya Hsu, Amanda Moffitt, Alissa Ren, Irene Tsaur, Samuel Wang:
Empirical study on sufficient numbers of minimum cuts in strongly connected directed random graphs. Networks 76(1): 106-121 (2020) - [j81]Xinyuan Wang, Pengwen Chen, Chung-Kuan Cheng:
Stability and Convergency Exploration of Matrix Exponential Integration on Power Delivery Network Transient Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2735-2748 (2020) - [j80]Dongwon Park, Daeyeal Lee, Ilgweon Kang, Chester Holtz, Sicun Gao, Bill Lin, Chung-Kuan Cheng:
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5097-5110 (2020) - [c195]Dongwon Park, Daeyeal Lee, Ilgweon Kang, Sicun Gao, Bill Lin, Chung-Kuan Cheng:
SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm. ASP-DAC 2020: 345-350 - [c194]Po-Ya Hsu, Chung-Kuan Cheng:
Arrhythmia Classification using Deep Learning and Machine Learning with Features Extracted from Waveform-based Signal Processing. EMBC 2020: 292-295 - [c193]Po-Ya Hsu, Chung-Kuan Cheng:
R-peak Detection Using a Hybrid of Gaussian and Threshold Sensitivity. EMBC 2020: 4470-4474 - [c192]Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park:
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT. ICCAD 2020: 158:1-158:8 - [c191]Chung-Kuan Cheng, Daeyeal Lee, Dongwon Park:
Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility. ISCAS 2020: 1-5 - [i7]Pengwen Chen, Chung-Kuan Cheng, Xinyuan Wang:
Arnoldi algorithms with structured orthogonalization. CoRR abs/2005.14468 (2020)
2010 – 2019
- 2019
- [j79]Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Lutong Wang:
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1717-1730 (2019) - [j78]Ilgweon Kang, Fang Qiao, Dongwon Park, Daniel Kane, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham:
Three-dimensional Floorplan Representations by Using Corner Links and Partial Order. ACM Trans. Design Autom. Electr. Syst. 24(1): 13:1-13:33 (2019) - [c190]Eric Chang, Chung-Kuan Cheng, Anushka Gupta, Po-Han Hsu, Po-Ya Hsu, Hsin-Li Liu, Amanda Moffitt, Alissa Ren, Irene Tsaur, Samuel Wang:
Cuff-Less Blood Pressure Monitoring with a 3-Axis Accelerometer. EMBC 2019: 6834-6837 - [c189]Dongwon Park, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng:
ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques. ISPD 2019: 65-72 - 2018
- [c188]Ilgweon Kang, Dongwon Park, Changho Han, Chung-Kuan Cheng:
Fast and precise routability analysis with conditional design rules. SLIP@DAC 2018: 4:1-4:8 - [c187]Po-Ya Hsu, Chun-Han Yao, Yuwei Wang, Chung-Kuan Cheng:
Adaptive sensitivity analysis with nonlinear power load modeling. SLIP@DAC 2018: 5:1-5:6 - [c186]Pengwen Chen, Chung-Kuan Cheng, Dongwon Park, Xinyuan Wang:
Transient circuit simulation for differential algebraic systems using matrix exponential. ICCAD 2018: 99 - [c185]Chung-Kuan Cheng, Ronald L. Graham, Ilgweon Kang, Dongwon Park, Xinyuan Wang:
Tree Structures and Algorithms for Physical Design. ISPD 2018: 120-125 - [c184]Chung-Kuan Cheng, T. C. Hu, Andrew B. Kahng:
Theory and Algorithms of Physical Design. ISPD 2018: 130-131 - 2017
- [c183]Xinyuan Wang, Hao Zhuang, Chung-Kuan Cheng:
Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulation. ICCAD 2017: 163-168 - [c182]Ilgweon Kang, Chung-Kuan Cheng:
Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond. ISPD 2017: 123-128 - 2016
- [j77]Quan Chen, Wim Schoenmaker, Shih-Hung Weng, Chung-Kuan Cheng, Guan-Hua Chen, Lijun Jiang, Ngai Wong:
A fast time-domain EM-TCAD coupled simulation framework via matrix exponential with stiffness reduction. Int. J. Circuit Theory Appl. 44(4): 833-850 (2016) - [j76]Qinggao Mei, Wim Schoenmaker, Shih-Hung Weng, Hao Zhuang, Chung-Kuan Cheng, Quan Chen:
An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 832-843 (2016) - [j75]Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, Chung-Kuan Cheng:
Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1681-1694 (2016) - [c181]Fang Qiao, Ilgweon Kang, Daniel Kane, Fung Yu Young, Chung-Kuan Cheng, Ronald L. Graham:
3D floorplan representations: Corner links and partial order. 3DIC 2016: 1-5 - [c180]Jingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen, Chung-Kuan Cheng:
ePlace-3D: Electrostatics based Placement for 3D-ICs. ISPD 2016: 11-18 - 2015
- [j74]Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis J.-H. Huang, Yufeng Luo, Chin-Chi Teng, Chung-Kuan Cheng:
ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 685-698 (2015) - [j73]Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng:
ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method. ACM Trans. Design Autom. Electr. Syst. 20(2): 17:1-17:34 (2015) - [c179]Jeng-Hau Lin, Hao Liu, Chia-Hung Liu, Phillip Lam, Gung-Yu Pan, Hao Zhuang, Ilgweon Kang, Patrick P. Mercier, Chung-Kuan Cheng:
An interdigitated non-contact ECG electrode for impedance compensation and signal restoration. BioCAS 2015: 1-4 - [c178]Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng:
An algorithmic framework for efficient large-scale circuit simulation using exponential integrators. DAC 2015: 163:1-163:6 - [c177]Yu-Te Wang, Masaki Nakanishi, Simon Lind Kappel, Preben Kidmose, Danilo P. Mandic, Yijun Wang, Chung-Kuan Cheng, Tzyy-Ping Jung:
Developing an online steady-state visual evoked potential-based brain-computer interface system using EarEEG. EMBC 2015: 2271-2274 - [c176]Xiang Zhang, Yang Liu, Ryan Coutts, Chung-Kuan Cheng:
Power line communication for hybrid power/signal pin SOC design. SLIP 2015: 1-8 - [i6]Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, Jingwei Lu, Chung-Kuan Cheng:
Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks. CoRR abs/1505.06699 (2015) - [i5]Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng:
An Algorithmic Framework for Efficient Large-Scale Circuit Simulation Using Exponential Integrators. CoRR abs/1511.04515 (2015) - [i4]Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng:
MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks. CoRR abs/1511.04519 (2015) - [i3]Jingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen, Chung-Kuan Cheng:
ePlace-3D: Electrostatics based Placement for 3D-ICs. CoRR abs/1512.08291 (2015) - 2014
- [j72]Xiang Hu, Peng Du, Shih-Hung Weng, Chung-Kuan Cheng:
Worst Case Noise Prediction With Nonzero Current Transition Times for Power Grid Planning. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 607-620 (2014) - [j71]Shih-Hung Weng, Yulei Zhang, James F. Buckwalter, Chung-Kuan Cheng:
Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 938-942 (2014) - [c175]Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng:
MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks. DAC 2014: 81:1-81:6 - [c174]Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis J.-H. Huang, Chin-Chi Teng, Chung-Kuan Cheng:
ePlace: Electrostatics Based Placement Using Nesterov's Method. DAC 2014: 121:1-121:6 - [c173]Xiang Zhang, Jingwei Lu, Yang Liu, Chung-Kuan Cheng:
Worst-case noise area prediciton of on-chip power distribution network. SLIP 2014: 2:1-2:8 - 2013
- [j70]Xiang Hu, Peng Du, James F. Buckwalter, Chung-Kuan Cheng:
Modeling and Analysis of Power Distribution Networks in 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 354-366 (2013) - [c172]Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng:
FFTPL: An analytic placement algorithm using fast fourier transform for density equalization. ASICON 2013: 1-4 - [c171]Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng:
Power grid simulation using matrix exponential method with rational Krylov subspaces. ASICON 2013: 1-4 - [c170]Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng:
Layer minimization in escape routing for staggered-pin-array PCBs. ASP-DAC 2013: 187-192 - [c169]Liya Huang, Xiaoxia Huang, Yu-Te Wang, Yijun Wang, Tzyy-Ping Jung, Chung-Kuan Cheng:
Empirical mode decomposition improves detection of SSVEP. EMBC 2013: 3901-3904 - [c168]Yu-Te Wang, Yijun Wang, Chung-Kuan Cheng, Tzyy-Ping Jung:
Developing stimulus presentation on mobile devices for a truly portable SSVEP-based BCI. EMBC 2013: 5271-5274 - [c167]Xiang Zhang, Yang Liu, Chung-Kuan Cheng:
Worst-case noise prediction using power network impedance profile. SLIP 2013: 1-8 - [i2]Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng:
Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces. CoRR abs/1309.5333 (2013) - [i1]Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng:
FFTPL: An Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization. CoRR abs/1312.4587 (2013) - 2012
- [j69]Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong:
A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(1): 109-120 (2012) - [j68]Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong:
Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 452 (2012) - [j67]Quan Chen, Shih-Hung Weng, Chung-Kuan Cheng:
A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 1031-1040 (2012) - [j66]Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng:
Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8): 1180-1193 (2012) - [c166]Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald L. Graham:
Character design and stamp algorithms for Character Projection Electron-Beam Lithography. ASP-DAC 2012: 725-730 - [c165]Yu-Te Wang, Chung-Kuan Cheng, Kuan-Chih Huang, Chin-Teng Lin, Yijun Wang, Tzyy-Ping Jung:
Cell-phone based Drowsiness Monitoring and Management system. BioCAS 2012: 200-203 - [c164]Yu-Te Wang, Yijun Wang, Chung-Kuan Cheng, Tzyy-Ping Jung:
Measuring Steady-State Visual Evoked Potentials from non-hair-bearing areas. EMBC 2012: 1806-1809 - [c163]Shih-Hung Weng, Quan Chen, Ngai Wong, Chung-Kuan Cheng:
Circuit simulation via matrix exponential method for stiffness handling and parallel processing. ICCAD 2012: 407-414 - [c162]Quan Chen, Wim Schoenmaker, Shih-Hung Weng, Chung-Kuan Cheng, Guan-Hua Chen, Lijun Jiang, Ngai Wong:
A fast time-domain EM-TCAD coupled simulation framework via matrix exponential. ICCAD 2012: 422-428 - [c161]Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng:
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph. ISPD 2012: 105-112 - [c160]Ying-Chi Li, Quan Chen, Shih-Hung Weng, Chung-Kuan Cheng, Ngai Wong:
Globally stable, highly parallelizable fast transient circuit simulation via faber series. NEWCAS 2012: 177-180 - [c159]Guang Sun, Shih-Hung Weng, Chung-Kuan Cheng, Bill Lin, Lieguang Zeng:
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era. SLIP 2012: 11-18 - 2011
- [j65]Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham:
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 167-179 (2011) - [j64]Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng:
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 520-524 (2011) - [j63]Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng:
Prediction and Comparison of High-Performance On-Chip Global Interconnection. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1154-1166 (2011) - [c158]Peng Du, Shih-Hung Weng, Xiang Hu, Chung-Kuan Cheng:
Power grid sizing via convex programming. ASICON 2011: 337-340 - [c157]Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng:
Circuit simulation using matrix exponential method. ASICON 2011: 369-372 - [c156]Amirali Shayan Arani, Xiang Hu, Chung-Kuan Cheng, Wenjian Yu, Christopher Pan:
Linear Dropout Regulator based power distribution design under worst loading. ASICON 2011: 539-542 - [c155]Xiang Hu, Peng Du, Chung-Kuan Cheng:
Exploring 3D power distribution network physics. ASICON 2011: 562-565 - [c154]Zheng Zhang, Xiang Hu, Chung-Kuan Cheng, Ngai Wong:
A block-diagonal structured model reduction scheme for power grid networks. DATE 2011: 44-49 - [c153]Shih-Hung Weng, Peng Du, Chung-Kuan Cheng:
A fast and stable explicit integration method by matrix exponential operator for large scale circuit simulation. ISCAS 2011: 1467-1470 - [c152]Chung-Kuan Cheng:
Placement and beyond in honor of Ernest S. Kuh. ISPD 2011: 5-8 - [c151]Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong:
More realistic power grid verification based on hierarchical current and power constraints. ISPD 2011: 159-166 - 2010
- [j62]Shan Zeng, Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng:
Efficient Power Network Analysis with Modeling of Inductive Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(6): 1196-1203 (2010) - [j61]Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng:
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness. ACM Trans. Design Autom. Electr. Syst. 15(4): 33:1-33:22 (2010) - [c150]Xiang Hu, Thomas Toms, Riko Radojcic, Matt Nowak, Nick Yu, Chung-Kuan Cheng:
Enabling power distribution network analysis flows for 3D ICs. 3DIC 2010: 1-4 - [c149]Wanping Zhang, Ling Zhang, Amirali Shayan Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Ege Engin, Chung-Kuan Cheng:
On-chip power network optimization with decoupling capacitors and controlled-ESRs. ASP-DAC 2010: 119-124 - [c148]Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Arani, Chung-Kuan Cheng:
An adaptive parallel flow for power distribution network simulation using discrete Fourier transform. ASP-DAC 2010: 125-130 - [c147]Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng:
Bus via reduction based on floorplan revising. ACM Great Lakes Symposium on VLSI 2010: 9-14 - [c146]Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng:
Physical synthesis of bus matrix for high bandwidth low power on-chip communications. ISPD 2010: 91-96 - [c145]Peng Du, Xiang Hu, Shih-Hung Weng, Amirali Shayan Arani, Xiaoming Chen, A. Ege Engin, Chung-Kuan Cheng:
Worst-case noise prediction with non-zero current transition times for early power distribution system verification. ISQED 2010: 624-631 - [c144]Yulei Zhang, James F. Buckwalter, Chung-Kuan Cheng:
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling. SLIP 2010: 69-76 - [c143]Chung-Kuan Cheng, Andrew B. Kahng, Kambiz Samadi, Amirali Shayan Arani:
Worst-case performance prediction under supply voltage and temperature variation. SLIP 2010: 91-96
2000 – 2009
- 2009
- [j60]Wenjian Yu, Rui Shi, Chung-Kuan Cheng:
Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design. IEICE Trans. Electron. 92-C(4): 444-452 (2009) - [j59]Shan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng:
Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1476-1484 (2009) - [j58]Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng:
Efficient Power Network Analysis Considering Multidomain Clock Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1348-1358 (2009) - [j57]Yi Zhu, Thomas Weng, Chung-Kuan Cheng:
Enhancing Learning Effectiveness in Digital Design Courses Through the Use of Programmable Logic Boards. IEEE Trans. Educ. 52(1): 151-156 (2009) - [j56]Yi Zhu, Yuanfang Hu, Michael B. Taylor, Chung-Kuan Cheng:
Energy and switch area optimizations for FPGA global routing architectures. ACM Trans. Design Autom. Electr. Syst. 14(1): 13:1-13:25 (2009) - [c142]