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ORCIDMartin D. F. Wong
D. F. Wong 0001
Person information
- affiliation: University of Illinois at Urbana-Champaign, IL, USA
- affiliation: University of Texas at Austin, TX, USA
- affiliation (PhD 1987): University of Illinois at Urbana-Champaign, IL, USA
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2020 – today
- 2023
[j117]Shiju Lin
, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong:
GAMER: GPU-Accelerated Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 583-593 (2023)- [i2]Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields. CoRR abs/2303.08435 (2023) - [i1]Wenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu, Martin D. F. Wong:
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU. CoRR abs/2303.08999 (2023) - 2022
- [c304]Shiju Lin, Jinwei Liu, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young:
NovelRewrite: node-level parallel AIG rewriting. DAC 2022: 427-432 - [c303]Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young:
Partition and place finite element model on wafer-scale engine. DAC 2022: 631-636 - [c302]Qijing Wang, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young:
A2-ILT: GPU accelerated ILT with spatial attention mechanism. DAC 2022: 967-972 - [c301]Lixin Liu, Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young:
Xplace: an extremely fast and extensible global placement framework. DAC 2022: 1309-1314 - [c300]Shiju Lin, Martin D. F. Wong:
Superfast Full-Scale CPU-Accelerated Global Routing. ICCAD 2022: 51 - [c299]Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
AdaOPC: A Self-Adaptive Mask Optimization Framework for Real Design Patterns. ICCAD 2022: 123 - [c298]Qijing Wang, Martin D. F. Wong:
WaferHSL: Wafer Failure Pattern Classification with Efficient Human-Like Staged Learning. ICCAD 2022: 125 - [c297]Xinshi Zang, Fangzhou Wang, Jinwei Liu, Martin D. F. Wong:
ATLAS: A Two-Level Layer-Aware Scheme for Routing with Cell Movement. ICCAD 2022: 128 - [c296]Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong:
Efficient Design Rule Checking Script Generation via Key Information Extraction. MLCAD 2022: 77-82 - [p2]S. T. Choden Konigsmark, Wei Ren, Martin D. F. Wong, Deming Chen:
High-Level Synthesis for Minimizing Power Side-Channel Information Leakage. Behavioral Synthesis for Hardware Security 2022: 291-317 - 2021
- [j116]Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong:
OpenTimer v2: A Parallel Incremental Timing Analysis Engine. IEEE Des. Test 38(2): 62-68 (2021) - [j115]Tsung-Wei Huang, Guannan Guo, Chun-Xun Lin, Martin D. F. Wong:
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 776-789 (2021) - [j114]Tsung-Wei Huang, Yibo Lin, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong:
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1687-1700 (2021) - [c295]Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong:
GPU-accelerated Path-based Timing Analysis. DAC 2021: 721-726 - [c294]Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework. ICCAD 2021: 1-9 - [c293]Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong:
GPU-accelerated Critical Path Generation with Path Constraints. ICCAD 2021: 1-9 - [c292]Shiju Lin, Jinwei Liu, Martin D. F. Wong:
GAMER: GPU Accelerated Maze Routing. ICCAD 2021: 1-8 - [c291]Fangzhou Wang, Lixin Liu, Jingsong Chen, Jinwei Liu, Xinshi Zang, Martin D. F. Wong:
Starfish: An Efficient P&R Co-Optimization Engine with A*-based Partial Rerouting. ICCAD 2021: 1-9 - [c290]Wenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu, Martin D. F. Wong:
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU. ICCAD 2021: 1-9 - [c289]Dan Zheng, Xinshi Zang, Martin D. F. Wong:
TopoPart: a Multi-level Topology-Driven Partitioning Framework for Multi-FPGA Systems. ICCAD 2021: 1-8 - [c288]Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu, Martin D. F. Wong:
Hotspot Detection via Multi-task Learning and Transformer Encoder. ICCAD 2021: 1-8 - 2020
- [j113]Daifeng Guo, Hongbo Zhang, Martin D. F. Wong:
On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1205-1216 (2020) - [c287]Guannan Guo, Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong:
An Efficient Critical Path Generation Algorithm Considering Extensive Path Constraints. DAC 2020: 1-6 - [c286]Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, Martin D. F. Wong:
Learn to Floorplan through Acquisition of Effective Local Search Heuristics. ICCD 2020: 324-331 - [c285]Chun-Xun Lin, Tsung-Wei Huang, Martin D. F. Wong:
An Efficient Work-Stealing Scheduler for Task Dependency Graph. ICPADS 2020: 64-71
2010 – 2019
- 2019
- [j112]Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong:
DtCraft: A High-Performance Distributed Execution Engine at Scale. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1070-1083 (2019) - [c284]Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong:
Essential Building Blocks for Creating an Open-source EDA Project. DAC 2019: 78 - [c283]Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong:
Distributed Timing Analysis at Scale. DAC 2019: 229 - [c282]Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong:
An Efficient and Composable Parallel Task Programming Library. HPEC 2019: 1-7 - [c281]Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong:
Cpp-Taskflow: Fast Task-Based Parallel Programming Using Modern C++. IPDPS 2019: 974-983 - [c280]Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong:
A Modern C++ Parallel Task Programming Library. ACM Multimedia 2019: 2284-2287 - 2018
- [c279]Tin-Yin Lai, Martin D. F. Wong:
A highly compressed timing macro-modeling algorithm for hierarchical and incremental timing analysis. ASP-DAC 2018: 166-171 - [c278]Daifeng Guo, Hongbo Zhang, Martin D. F. Wong:
On coloring rectangular and diagonal grid graphs for multiple patterning lithography. ASP-DAC 2018: 387-392 - [c277]Chun-Xun Lin, Martin D. F. Wong:
Accelerate analytical placement with GPU: A generic approach. DATE 2018: 1345-1350 - [c276]Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong:
MtDetector: A High-performance Marine Traffic Detector at Stream Scale. DEBS 2018: 205-208 - [c275]Chun-Xun Lin, Tsung-Wei Huang, Ting Yu, Martin D. F. Wong:
A Distributed Power Grid Analysis Framework from Sequential Stream Graph. ACM Great Lakes Symposium on VLSI 2018: 183-188 - [c274]Chun-Xun Lin, Tsung-Wei Huang, Martin D. F. Wong:
Routing at compile time. ISQED 2018: 169-175 - [c273]Leslie Hwang, Beomjin Kwon, Martin D. F. Wong:
Accurate Models for Optimizing Tapered Microchannel Heat Sinks in 3D ICs. ISVLSI 2018: 58-63 - [c272]Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong:
A General-purpose Distributed Programming System using Data-parallel Streams. ACM Multimedia 2018: 1360-1363 - 2017
- [c271]S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong:
High-Level Synthesis for side-channel defense. ASAP 2017: 37-44 - [c270]Tin-Yin Lai, Tsung-Wei Huang, Martin D. F. Wong:
LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs. DAC 2017: 65:1-65:6 - [c269]Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong:
DtCraft: A distributed execution engine for compute-intensive applications. ICCAD 2017: 757-765 - 2016
- [j111]Sven Tenzing Choden Konigsmark, Deming Chen, Martin D. F. Wong:
PolyPUF: Physically Secure Self-Divergence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1053-1066 (2016) - [j110]Tsung-Wei Huang, Martin D. F. Wong:
UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPR. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1862-1875 (2016) - [c268]Zigang Xiao, Chun-Xun Lin, Martin D. F. Wong, Hongbo Zhang:
Contact layer decomposition to enable DSA with multi-patterning technique for standard cell based layout. ASP-DAC 2016: 95-102 - [c267]S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong:
Information dispersion for trojan defense through high-level synthesis. DAC 2016: 87:1-87:6 - [c266]Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran:
A distributed timing analysis framework for large designs. DAC 2016: 116:1-116:6 - [c265]Martin D. F. Wong:
Early Days of Automatic Floorplan Design. ISPD 2016: 107 - [c264]Haitong Tian, Martin D. F. Wong:
Performance evaluation considering mask misalignment in multiple patterning decomposition. ISQED 2016: 192-197 - [r5]Martin D. F. Wong, Hannah Honghua Yang:
Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach. Encyclopedia of Algorithms 2016: 295-301 - [r4]Haitong Tian, Martin D. F. Wong:
Layout Decomposition for Multiple Patterning. Encyclopedia of Algorithms 2016: 1059-1062 - 2015
- [j109]Fan Zhang, Chen Hu, Pei-Ci Wu, Hongbo Zhang, Martin D. F. Wong:
Accelerating aerial image simulation using improved CPU/GPU collaborative computing. Comput. Electr. Eng. 46: 176-189 (2015) - [c263]Haitong Tian, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong:
An efficient linear time triple patterning solver. ASP-DAC 2015: 208-213 - [c262]Zigang Xiao, Yuelin Du, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang:
Contact pitch and location prediction for Directed Self-Assembly template verification. ASP-DAC 2015: 644-651 - [c261]Daifeng Guo, Yuelin Du, Martin D. F. Wong:
Polynomial time optimal algorithm for stencil row planning in e-beam lithography. ASP-DAC 2015: 658-664 - [c260]Zigang Xiao, Daifeng Guo, Martin D. F. Wong, He Yi, Maryann C. Tung, H.-S. Philip Wong:
Layout optimization and template pattern verification for directed self-assembly (DSA). DAC 2015: 199:1-199:6 - [c259]Tsung-Wei Huang, Martin D. F. Wong:
OpenTimer: A High-Performance Timing Analysis Tool. ICCAD 2015: 895-902 - [c258]Tsung-Wei Huang, Martin D. F. Wong:
Accelerated Path-Based Timing Analysis with MapReduce. ISPD 2015: 103-110 - [c257]Martin D. F. Wong:
Early Days of Circuit Placement. ISPD 2015: 129 - [c256]Tsung-Wei Huang, Martin D. F. Wong:
On fast timing closure: speeding up incremental path-based timing analysis with mapreduce. SLIP 2015: 1-6 - 2014
- [c255]S. T. Choden Konigsmark, Leslie Hwang, Deming Chen, Martin D. F. Wong:
CNPUF: A Carbon Nanotube-based Physically Unclonable Function for secure low-energy hardware design. ASP-DAC 2014: 73-78 - [c254]Ting Yu, Martin D. F. Wong:
Efficient simulation-based optimization of power grid with on-chip voltage regulator. ASP-DAC 2014: 531-536 - [c253]S. T. Choden Konigsmark, Leslie K. Hwang, Deming Chen, Martin D. F. Wong:
System-of-PUFs: Multilevel security for embedded systems. CODES+ISSS 2014: 27:1-27:10 - [c252]Pei-Ci Wu, Martin D. F. Wong, Ivailo Nedelchev, Sarvesh Bhardwaj, Vidyamani Parkhe:
On Timing Closure: Buffer Insertion for Hold-Violation Removal. DAC 2014: 6:1-6:6 - [c251]Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang:
Directed Self-Assembly (DSA) Template Pattern Verification. DAC 2014: 55:1-55:6 - [c250]Yuelin Du, Martin D. F. Wong:
Optimization of standard cell based detailed placement for 16 nm FinFET process. DATE 2014: 1-6 - [c249]Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong:
Triple patterning aware detailed placement with constrained pattern assignment. ICCAD 2014: 116-123 - [c248]Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong:
Fast path-based timing analysis for CPPR. ICCAD 2014: 596-599 - [c247]Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong:
UI-timer: an ultra-fast clock network pessimism removal algorithm. ICCAD 2014: 758-765 - [c246]Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong:
UI-route: An ultra-fast incremental maze routing algorithm. SLIP 2014: 4:1-4:8 - 2013
- [j108]Zigang Xiao, Yuelin Du, Hongbo Zhang, Martin D. F. Wong:
A Polynomial Time Exact Algorithm for Overlay-Resistant Self-Aligned Double Patterning (SADP) Layout Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1228-1239 (2013) - [j107]Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong, Deming Chen:
A routing algorithm for graphene nanoribbon circuit. ACM Trans. Design Autom. Electr. Syst. 18(4): 61:1-61:18 (2013) - [c245]Ismail Bustany, Igor L. Markov, Martin D. F. Wong:
The nature of optimization problem challenges in physical synthesis. ACC 2013: 6057-6059 - [c244]Pei-Ci Wu, Qiang Ma, Martin D. F. Wong:
An ILP-based automatic bus planner for dense PCBs. ASP-DAC 2013: 181-186 - [c243]Pei-Ci Wu, Martin D. F. Wong:
Network flow modeling for escape routing on staggered pin arrays. ASP-DAC 2013: 193-198 - [c242]Yuelin Du, Hongbo Zhang, Qiang Ma, Martin D. F. Wong:
Linear time algorithm to find all relocation positions for EUV defect mitigation. ASP-DAC 2013: 261-266 - [c241]Yuelin Du, Qiang Ma, Hua Song, James P. Shiely, Gerard Luk-Pat, Alexander Miloslavsky, Martin D. F. Wong:
Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography. DAC 2013: 93:1-93:6 - [c240]Pei-Ci Wu, Tan Yan, Hongbo Zhang, Martin D. F. Wong:
Efficient aerial image simulation on multi-core SIMD CPU. ICCAD 2013: 24-31 - [c239]Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong:
Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time. ICCAD 2013: 32-39 - [c238]Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong:
Constrained pattern assignment for standard cell based triple patterning lithography. ICCAD 2013: 178-185 - [c237]Yuelin Du, Daifeng Guo, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang, Qiang Ma:
Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library. ICCAD 2013: 186-193 - [c236]Ting Yu, Martin D. F. Wong:
A novel and efficient method for power pad placement optimization. ISQED 2013: 158-163 - [c235]Martin D. F. Wong:
Advances in wire routing. ISQED 2013: 257 - 2012
- [j106]Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng:
A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 322-332 (2012) - [j105]Tan Yan, Qiang Ma, Martin D. F. Wong:
Advances in PCB Routing. IPSJ Trans. Syst. LSI Des. Methodol. 5: 14-22 (2012) - [j104]Tan Yan, Martin D. F. Wong:
Correctly Model the Diagonal Capacity in Escape Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 285-293 (2012) - [j103]Qiang Ma, Martin D. F. Wong:
NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1356-1365 (2012) - [c234]Lijuan Luo, Martin D. F. Wong, Lance Leong:
Parallel implementation of R-trees on the GPU. ASP-DAC 2012: 353-358 - [c233]Yuelin Du, Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao:
Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design. ASP-DAC 2012: 707-712 - [c232]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit Onur Topaloglu:
Efficient pattern relocation for EUV blank defect mitigation. ASP-DAC 2012: 719-724 - [c231]Qiang Ma, Hongbo Zhang, Martin D. F. Wong:
Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. DAC 2012: 591-596 - [c230]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Yunfei Deng, Pawitter Mangat:
Layout small-angle rotation and shift for EUV defect mitigation. ICCAD 2012: 43-49 - [c229]Haitong Tian, Hongbo Zhang, Qiang Ma, Zigang Xiao, Martin D. F. Wong:
A polynomial time triple patterning algorithm for cell based row-structure layout. ICCAD 2012: 57-64 - [c228]Ting Yu, Zigang Xiao, Martin D. F. Wong:
Efficient parallel power grid analysis via Additive Schwarz Method. ICCAD 2012: 399-406 - [c227]Ting Yu, Martin D. F. Wong:
PGT_SOLVER: An efficient solver for power grid transient analysis. ICCAD 2012: 647-652 - [c226]Zigang Xiao, Yuelin Du, Hongbo Zhang, Martin D. F. Wong:
A polynomial time exact algorithm for self-aligned double patterning layout decomposition. ISPD 2012: 17-24 - [c225]Martin D. F. Wong:
On simulated annealing in EDA. ISPD 2012: 63-64 - [c224]Leslie Hwang, Kevin L. Lin, Martin D. F. Wong:
Thermal via structural design in three-dimensional integrated circuits. ISQED 2012: 103-108 - [c223]Qiang Ma, Zigang Xiao, Martin D. F. Wong:
Algorithmic study on the routing reliability problem. ISQED 2012: 483-488 - [c222]Hongbo Zhang, Yunfei Deng, Jongwook Kye, Martin D. F. Wong:
Impact of lithography retargeting process on low level interconnect in 20nm technology. SLIP 2012: 3-10 - 2011
- [j102]Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya:
A New Strategy for Simultaneous Escape Based on Boundary Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 205-214 (2011) - [j101]Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang:
Thermal-Driven Analog Placement Considering Device Matching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 325-336 (2011) - [c221]Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong, Deming Chen:
Routing with graphene nanoribbons. ASP-DAC 2011: 323-329 - [c220]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao:
Mask cost reduction with circuit performance consideration for self-aligned double patterning. ASP-DAC 2011: 787-792 - [c219]Qiang Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young:
A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing. ASP-DAC 2011: 843-848 - [c218]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit Onur Topaloglu:
Self-aligned double patterning decomposition for overlay minimization and hot spot detection. DAC 2011: 71-76 - [c217]Qiang Ma, Evangeline F. Y. Young, Martin D. F. Wong:
An optimal algorithm for layer assignment of bus escape routing on PCBs. DAC 2011: 176-181 - [c216]Hongbo Zhang, Tan Yan, Martin D. F. Wong, Sanjay J. Patel:
Accelerating aerial image simulation with GPU. ICCAD 2011: 178-184 - [c215]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao:
Lithography-aware layout modification considering performance impact. ISQED 2011: 437-441 - 2010
- [j100]Quang Dinh, Deming Chen, Martin D. F. Wong:
A Routing Approach to Reduce Glitches in Low Power FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 235-240 (2010) - [c214]Hui Kong, Tan Yan, Martin D. F. Wong:
Optimal simultaneous pin assignment and escape routing for dense PCBs. ASP-DAC 2010: 275-280 - [c213]Qiang Ma, Martin D. F. Wong, Kai-Yuan Chao:
Configurable multi-product floorplanning. ASP-DAC 2010: 549-554 - [c212]Quang Dinh, Deming Chen, Martin D. F. Wong:
Dynamic power estimation for deep submicron circuits with process variation. ASP-DAC 2010: 587-592 - [c211]Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao:
On process-aware 1-D standard cell design. ASP-DAC 2010: 838-842 - [c210]Lijuan Luo, Martin D. F. Wong, Wen-mei W. Hwu:
An effective GPU implementation of breadth-first search. DAC 2010: 52-55 - [c209]Hui Kong, Qiang Ma, Tan Yan, Martin D. F. Wong:
An optimal algorithm for finding disjoint rectangles and its application to PCB routing. DAC 2010: 212-217 - [c208]Tan Yan, Martin D. F. Wong:
Recent research development in PCB layout. ICCAD 2010: 398-403 - [c207]Tan Yan, Pei-Ci Wu, Qiang Ma, Martin D. F. Wong:
On the escape routing of differential pairs.