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ORCIDRobert A. Walker 0001
Person information
- affiliation: Kent State University, OH, USA
- affiliation (1989 - 1996): Rensselaer Polytechnic Institute, Troy, NY, USA
- affiliation (PhD 1988): Carnegie-Mellon University, Pittsburgh, PA, USA
Other persons with the same name
- Robert A. Walker — disambiguation page
- Robert A. Walker 0002 — Naval Postgraduate School, Monterey, CA, USA
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2010 – 2019
- 2011
[c25]Kevin Schaffer, Robert A. Walker:
MTASC: A Multithreaded Associative SIMD Processor. IPDPS Workshops 2011: 1776-1780
2000 – 2009
- 2008
- [j8]Kevin Schaffer, Robert A. Walker:
Using Hardware Multithreading to Overcome Broadcast/Reduction Latency in an Associative SIMD Processor. Parallel Process. Lett. 18(4): 491-509 (2008) - [c24]Ken W. Batcher, Robert A. Walker:
Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems. DATE 2008: 260-263 - [c23]Kevin Schaffer, Robert A. Walker:
Using hardware multithreading to overcome broadcast/reduction latency in an associative SIMD processor. IPDPS 2008: 1-7 - 2007
- [c22]Kevin Schaffer, Robert A. Walker:
A Prototype Multithreaded Associative SIMD Processor. IPDPS 2007: 1-6 - 2006
- [c21]Ken W. Batcher, Robert A. Walker:
Interrupt Triggered Software Prefetching for Embedded CPU Instruction Cache. IEEE Real Time Technology and Applications Symposium 2006: 91-102 - 2005
- [c20]Hong Wang, Robert A. Walker:
A Scalable Pipelined Associative SIMD Array with Reconfigurable PE Interconnection Network for Embedded Applications. IASTED PDCS 2005: 667-673 - 2004
- [c19]Ken W. Batcher, Robert A. Walker:
Cluster miss prediction with prefetch on miss for embedded CPU instruction caches. CASES 2004: 24-34 - [c18]Kenneth W. Batcher, Robert A. Walker:
Cluster miss prediction for instruction caches in embedded networking applications. ACM Great Lakes Symposium on VLSI 2004: 358-363 - [c17]Hong Wang, Lei Xie, Meiduo Wu, Robert A. Walker:
A Scalable Associative Processor with Applications in Database and Image Processing. IPDPS 2004 - 2003
- [c16]Hong Wang, Robert A. Walker:
Implementing a Scalable ASC Processor. IPDPS 2003: 267 - 2002
- [c15]Meiduo Wu, Robert A. Walker, Jerry L. Potter:
Implementing Associative Search and Responder Resolution. IPDPS 2002 - 2001
- [c14]Robert A. Walker, Jerry L. Potter, Yanping Wang, Meiduo Wu:
Implementing Associative Processing: Rethinking EarlierArchitectural Decisions. IPDPS 2001: 195 - 2000
- [j7]Stephen A. Blythe, Robert A. Walker:
Efficient optimal design space characterization methodologies. ACM Trans. Design Autom. Electr. Syst. 5(3): 322-336 (2000)
1990 – 1999
- 1999
- [c13]Stephen A. Blythe, Robert A. Walker:
Efficiently Searching the Optimal Design Space. Great Lakes Symposium on VLSI 1999: 192- - [c12]Samit Chaudhuri, Robert A. Walker:
Bounding Algorithms for Design Space Exploration. Great Lakes Symposium on VLSI 1999: 234-235 - [c11]Robert A. Walker:
A practical one-semester "VLSI design" course for computer science (and other) majors. SIGCSE 1999: 237-241 - 1997
- [j6]Samit Chaudhuri, S. A. Blthye, Robert A. Walker:
A solution methodology for exact design space exploration in a three-dimensional design space. IEEE Trans. Very Large Scale Integr. Syst. 5(1): 69-81 (1997) - 1996
- [j5]Samit Chaudhuri, Robert A. Walker:
Computing lower bounds on functional units before scheduling. IEEE Trans. Very Large Scale Integr. Syst. 4(2): 273-279 (1996) - [c10]Stephen A. Blythe, Robert A. Walker:
Toward a Practical Methodology for Completely Characterizing the Optimal Design Space. ISSS 1996: 8-13 - 1995
- [j4]Robert A. Walker, Samit Chaudhuri:
Introduction to the Scheduling Problem. IEEE Des. Test Comput. 12(2): 60-69 (1995) - [c9]Samit Chaudhuri, Stephen A. Blythe, Robert A. Walker:
An exact methodology for scheduling in a 3D design space. ISSS 1995: 78-83 - 1994
- [j3]Samit Chaudhuri, Robert A. Walker, J. E. Mitchell:
Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 456-471 (1994) - [c8]Samit Chaudhuri, Robert A. Walker:
Computing lower bounds on functional units before scheduling. HLSS 1994: 36-41 - [c7]Samit Chaudhuri, Robert A. Walker:
ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis. VLSI Design 1994: 17-20 - 1993
- [c6]Samit Chaudhuri, Robert A. Walker, John Mitchell:
The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem. ICCD 1993: 25-29 - [c5]Ching-Tang Chang, Kenneth Rose, Robert A. Walker:
Cluster-Oriented Scheduling in Pipelined Data Path Syntesis. ICCD 1993: 374-378 - 1991
- [c4]Robert A. Walker, Shivkumar Ramabadran, Rajive Joshi, Steinar Flatland:
Increasing User Interaction During High-Level Synthesis. MICRO 1991: 133-142
1980 – 1989
- 1989
- [j2]Robert A. Walker, Donald E. Thomas:
Behavioral transformation for algorithmic level IC design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(10): 1115-1128 (1989) - 1988
- [c3]Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn:
The System Architect's Workbench. DAC 1988: 337-343 - 1985
- [c2]Robert A. Walker, Donald E. Thomas:
A model of design representation and synthesis. DAC 1985: 453-459 - 1983
- [j1]Donald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, Robert A. Walker:
Automatic Data Path Synthesis. Computer 16(12): 59-70 (1983) - [c1]Robert A. Walker, Donald E. Thomas:
Behavioral level transformation in the CMU-DA system. DAC 1983: 788-789
Coauthor Index
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