BibTeX record conf/aspdac/KimLK18

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@inproceedings{DBLP:conf/aspdac/KimLK18,
  author       = {Sunmean Kim and
                  Taeho Lim and
                  Seokhyeong Kang},
  editor       = {Youngsoo Shin},
  title        = {An optimal gate design for the synthesis of ternary logic circuits},
  booktitle    = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
                  2018, Jeju, Korea (South), January 22-25, 2018},
  pages        = {476--481},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASPDAC.2018.8297369},
  doi          = {10.1109/ASPDAC.2018.8297369},
  timestamp    = {Sat, 19 Oct 2019 20:37:09 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/KimLK18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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