BibTeX record conf/aspdac/NiitsuHHOSKYK13

• > Home > conf/aspdac/NiitsuHHOSKYK13

@inproceedings{DBLP:conf/aspdac/NiitsuHHOSKYK13,
  author       = {Kiichi Niitsu and
                  Naohiro Harigai and
                  Daiki Hirabayashi and
                  Daiki Oki and
                  Masato Sakurai and
                  Osamu Kobayashi and
                  Takahiro J. Yamaguchi and
                  Haruo Kobayashi},
  title        = {Design of a clock jitter reduction circuit using gated phase blending
                  between self-delayed clock edges},
  booktitle    = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
                  2013, Yokohama, Japan, January 22-25, 2013},
  pages        = {103--104},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ASPDAC.2013.6509577},
  doi          = {10.1109/ASPDAC.2013.6509577},
  timestamp    = {Tue, 21 Mar 2023 20:56:55 +0100},
  biburl       = {https://dblp.org/rec/conf/aspdac/NiitsuHHOSKYK13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}