BibTeX record conf/asscc/ChengWCCSCY14

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@inproceedings{DBLP:conf/asscc/ChengWCCSCY14,
  author       = {Chun{-}Yuan Cheng and
                  Jinn{-}Shyan Wang and
                  Pei{-}Yuan Chou and
                  Shiou{-}Ching Chen and
                  Chi{-}Tien Sun and
                  Yuan{-}Hua Chu and
                  Tzu{-}Yi Yang},
  title        = {A 3 MHz-to-1.8 GHz 94 {\(\mu\)}W-to-9.5 mW 0.0153-mm\({}^{\mbox{2}}\)
                  all-digital delay-locked loop in 65-nm {CMOS}},
  booktitle    = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2014, KaoHsiung,
                  Taiwan, November 10-12, 2014},
  pages        = {361--364},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ASSCC.2014.7008935},
  doi          = {10.1109/ASSCC.2014.7008935},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/asscc/ChengWCCSCY14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}