BibTeX record conf/dasip/TonnellierLGJGW16

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@inproceedings{DBLP:conf/dasip/TonnellierLGJGW16,
  author    = {Thibaud Tonnellier and
               Camille Leroux and
               Bertrand Le Gal and
               Christophe J{\'{e}}go and
               Benjamin Gadat and
               Nicolas Van Wambeke},
  title     = {Hardware architecture for lowering the error floor of {LTE} turbo
               codes},
  booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
               (DASIP), Rennes, France, October 12-14, 2016},
  pages     = {107--112},
  year      = {2016},
  crossref  = {DBLP:conf/dasip/2016},
  url       = {https://doi.org/10.1109/DASIP.2016.7853805},
  doi       = {10.1109/DASIP.2016.7853805},
  timestamp = {Sat, 19 Oct 2019 20:34:03 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/TonnellierLGJGW16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dasip/2016,
  title     = {2016 Conference on Design and Architectures for Signal and Image Processing
               (DASIP), Rennes, France, October 12-14, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7845248/proceeding},
  isbn      = {979-1-0922-7915-3},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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