BibTeX record conf/dsd/DeniziakWW16

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@inproceedings{DBLP:conf/dsd/DeniziakWW16,
  author    = {Stanislaw Deniziak and
               Mariusz Wisniewski and
               Karol Wieczorek},
  editor    = {Paris Kitsos},
  title     = {Synthesis of Multivalued Logical Networks for {FPGA} Implementations},
  booktitle = {2016 Euromicro Conference on Digital System Design, {DSD} 2016, Limassol,
               Cyprus, August 31 - September 2, 2016},
  pages     = {657--660},
  publisher = {{IEEE} Computer Society},
  year      = {2016},
  url       = {https://doi.org/10.1109/DSD.2016.107},
  doi       = {10.1109/DSD.2016.107},
  timestamp = {Sat, 19 Oct 2019 20:02:13 +0200},
  biburl    = {https://dblp.org/rec/conf/dsd/DeniziakWW16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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