BibTeX record conf/glvlsi/SeyediACUHV11

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@inproceedings{DBLP:conf/glvlsi/SeyediACUHV11,
  author       = {Azam Seyedi and
                  Adri{\`{a}} Armejach and
                  Adri{\'{a}}n Cristal and
                  Osman S. Unsal and
                  Ibrahim Hur and
                  Mateo Valero},
  editor       = {David Atienza and
                  Yuan Xie and
                  Jos{\'{e}} L. Ayala and
                  Ken S. Stevens},
  title        = {Circuit design of a dual-versioning {L1} data cache for optimistic
                  concurrency},
  booktitle    = {Proceedings of the 21st {ACM} Great Lakes Symposium on {VLSI} 2010,
                  Lausanne, Switzerland, May 2-6, 2011},
  pages        = {325--330},
  publisher    = {{ACM}},
  year         = {2011},
  url          = {https://doi.org/10.1145/1973009.1973074},
  doi          = {10.1145/1973009.1973074},
  timestamp    = {Sun, 02 Jun 2019 21:15:14 +0200},
  biburl       = {https://dblp.org/rec/conf/glvlsi/SeyediACUHV11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}