BibTeX record conf/hpca/ZuRLR19

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@inproceedings{DBLP:conf/hpca/ZuRLR19,
  author       = {Yazhou Zu and
                  Daniel Richins and
                  Charles Lefurgy and
                  Vijay Janapa Reddi},
  title        = {Fine-Tuning the Active Timing Margin {(ATM)} Control Loop for Maximizing
                  Multi-core Efficiency on an {IBM} {POWER} Server},
  booktitle    = {25th {IEEE} International Symposium on High Performance Computer Architecture,
                  {HPCA} 2019, Washington, DC, USA, February 16-20, 2019},
  pages        = {106--119},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/HPCA.2019.00031},
  doi          = {10.1109/HPCA.2019.00031},
  timestamp    = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl       = {https://dblp.org/rec/conf/hpca/ZuRLR19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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