BibTeX record conf/iolts/YoshimotoAKTYMYKY11

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@inproceedings{DBLP:conf/iolts/YoshimotoAKTYMYKY11,
  author       = {Shusuke Yoshimoto and
                  Takuro Amashita and
                  D. Kozuwa and
                  Taiga Takata and
                  Masayoshi Yoshimura and
                  Yusuke Matsunaga and
                  Hiroto Yasuura and
                  Hiroshi Kawaguchi and
                  Masahiko Yoshimoto},
  title        = {Multiple-bit-upset and single-bit-upset resilient 8T {SRAM} bitcell
                  layout with divided wordline structure},
  booktitle    = {17th {IEEE} International On-Line Testing Symposium {(IOLTS} 2011),
                  13-15 July, 2011, Athens, Greece},
  pages        = {151--156},
  publisher    = {{IEEE} Computer Society},
  year         = {2011},
  url          = {https://doi.org/10.1109/IOLTS.2011.5993829},
  doi          = {10.1109/IOLTS.2011.5993829},
  timestamp    = {Mon, 11 Mar 2024 15:42:29 +0100},
  biburl       = {https://dblp.org/rec/conf/iolts/YoshimotoAKTYMYKY11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}