BibTeX record conf/iscas/ChangZDL19

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@inproceedings{DBLP:conf/iscas/ChangZDL19,
  author       = {Sheng Chang and
                  Xiong Zhou and
                  Zhaoming Ding and
                  Qiang Li},
  title        = {A 12-bit 30MS/s {SAR} {ADC} with VCO-Based Comparator and Split-and-Recombination
                  Redundancy for Bypass Logic},
  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
                  Sapporo, Japan, May 26-29, 2019},
  pages        = {1--5},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/ISCAS.2019.8702448},
  doi          = {10.1109/ISCAS.2019.8702448},
  timestamp    = {Mon, 07 Sep 2020 18:12:13 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/ChangZDL19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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