BibTeX record conf/islped/ChenCHLPR12

• > Home > conf/islped/ChenCHLPR12

@inproceedings{DBLP:conf/islped/ChenCHLPR12,
  author       = {Yu{-}Ting Chen and
                  Jason Cong and
                  Hui Huang and
                  Chunyue Liu and
                  Raghu Prabhakar and
                  Glenn Reinman},
  editor       = {Naresh R. Shanbhag and
                  Massimo Poncino and
                  Pai H. Chou and
                  Ajith Amerasekera},
  title        = {Static and dynamic co-optimizations for blocks mapping in hybrid caches},
  booktitle    = {International Symposium on Low Power Electronics and Design, ISLPED'12,
                  Redondo Beach, CA, {USA} - July 30 - August 01, 2012},
  pages        = {237--242},
  publisher    = {{ACM}},
  year         = {2012},
  url          = {https://doi.org/10.1145/2333660.2333717},
  doi          = {10.1145/2333660.2333717},
  timestamp    = {Tue, 06 Nov 2018 16:59:20 +0100},
  biburl       = {https://dblp.org/rec/conf/islped/ChenCHLPR12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}