BibTeX record conf/isscc/GonzalezFDHRPFS17

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@inproceedings{DBLP:conf/isscc/GonzalezFDHRPFS17,
  author    = {Christopher J. Gonzalez and
               Eric Fluhr and
               Daniel Dreps and
               David Hogenmiller and
               Rahul M. Rao and
               Jose Paredes and
               Michael S. Floyd and
               Michael A. Sperling and
               Ryan Kruse and
               Vinod Ramadurai and
               Ryan Nett and
               Md. Saiful Islam and
               Juergen Pille and
               Donald W. Plass},
  title     = {3.1 POWER9{\texttrademark}: {A} processor family optimized for cognitive
               computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4},
  booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  pages     = {50--51},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {https://doi.org/10.1109/ISSCC.2017.7870255},
  doi       = {10.1109/ISSCC.2017.7870255},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/GonzalezFDHRPFS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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