BibTeX record conf/isscc/KhwaCLSYSLCLYC18

• > Home > conf/isscc/KhwaCLSYSLCLYC18

@inproceedings{DBLP:conf/isscc/KhwaCLSYSLCLYC18,
  author       = {Win{-}San Khwa and
                  Jia{-}Jing Chen and
                  Jia{-}Fang Li and
                  Xin Si and
                  En{-}Yu Yang and
                  Xiaoyu Sun and
                  Rui Liu and
                  Pai{-}Yu Chen and
                  Qiang Li and
                  Shimeng Yu and
                  Meng{-}Fan Chang},
  title        = {A 65nm 4Kb algorithm-dependent computing-in-memory {SRAM} unit-macro
                  with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for
                  binary {DNN} edge processors},
  booktitle    = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2018, San Francisco, CA, USA, February 11-15, 2018},
  pages        = {496--498},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/ISSCC.2018.8310401},
  doi          = {10.1109/ISSCC.2018.8310401},
  timestamp    = {Wed, 26 Jul 2023 07:50:19 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/KhwaCLSYSLCLYC18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}