BibTeX record conf/isscc/LiSKSKCDMZLLPSH15

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@inproceedings{DBLP:conf/isscc/LiSKSKCDMZLLPSH15,
  author       = {Penny Li and
                  Jinuk Luke Shin and
                  Georgios K. Konstadinidis and
                  Francis Schumacher and
                  Venkatram Krishnaswamy and
                  Hoyeol Cho and
                  Sudesna Dash and
                  Robert P. Masleid and
                  Chaoyang Zheng and
                  Yuanjung David Lin and
                  Paul Loewenstein and
                  Heechoul Park and
                  Vijay Srinivasan and
                  Dawei Huang and
                  Changku Hwang and
                  Wenjay Hsu and
                  Curtis McAllister},
  title        = {4.2 {A} 20nm 32-Core 64MB {L3} cache {SPARC} {M7} processor},
  booktitle    = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2015, Digest of Technical Papers, San Francisco, CA, USA, February
                  22-26, 2015},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/ISSCC.2015.7062931},
  doi          = {10.1109/ISSCC.2015.7062931},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LiSKSKCDMZLLPSH15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}