BibTeX record conf/isscc/PilleWWSPFBTEPHRC10

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@inproceedings{DBLP:conf/isscc/PilleWWSPFBTEPHRC10,
  author    = {J{\"{u}}rgen Pille and
               Dieter F. Wendel and
               Otto Wagner and
               Rolf Sautter and
               Wolfgang Penth and
               Thomas Fr{\"{o}}hnel and
               Stefan B{\"{u}}ttner and
               Otto A. Torreiter and
               Martin Eckert and
               Jose Paredes and
               David Hrusecky and
               David Ray and
               Miles Canada},
  title     = {A 32kB 2R/1W {L1} data cache in 45nm {SOI} technology for the {POWER7TM}
               processor},
  booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
               Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
               2010},
  pages     = {344--345},
  publisher = {{IEEE}},
  year      = {2010},
  url       = {https://doi.org/10.1109/ISSCC.2010.5433849},
  doi       = {10.1109/ISSCC.2010.5433849},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/PilleWWSPFBTEPHRC10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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