BibTeX record conf/isvlsi/DasK17

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@inproceedings{DBLP:conf/isvlsi/DasK17,
  author       = {Shirshendu Das and
                  Hemangee K. Kapoor},
  title        = {Latency Aware Block Replacement for {L1} Caches in Chip Multiprocessor},
  booktitle    = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
                  Bochum, Germany, July 3-5, 2017},
  pages        = {182--187},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISVLSI.2017.40},
  doi          = {10.1109/ISVLSI.2017.40},
  timestamp    = {Fri, 24 Mar 2023 00:02:41 +0100},
  biburl       = {https://dblp.org/rec/conf/isvlsi/DasK17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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