BibTeX record conf/memsys/ShangLSSY19

download as .bib file

@inproceedings{DBLP:conf/memsys/ShangLSSY19,
  author       = {Xiaojing Shang and
                  Ming Ling and
                  Shan Shen and
                  Tianxiang Shao and
                  Jun Yang},
  title        = {{RRS} cache: a low voltage cache based on timing speculation {SRAM}
                  with a reuse-aware cacheline remapping mechanism},
  booktitle    = {Proceedings of the International Symposium on Memory Systems, {MEMSYS}
                  2019, Washington, DC, USA, September 30 - October 03, 2019},
  pages        = {451--458},
  publisher    = {{ACM}},
  year         = {2019},
  url          = {https://doi.org/10.1145/3357526.3357535},
  doi          = {10.1145/3357526.3357535},
  timestamp    = {Thu, 09 Jan 2020 16:23:36 +0100},
  biburl       = {https://dblp.org/rec/conf/memsys/ShangLSSY19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics