BibTeX record conf/parelec/Yang00a

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@inproceedings{DBLP:conf/parelec/Yang00a,
  author       = {Laurence Tianruo Yang},
  title        = {Parallel Efficient Implementation of Hierarchical Algorithms for Module
                  Placement of Large Chips},
  booktitle    = {2000 International Conference on Parallel Computing in Electrical
                  Engineering {(PARELEC} 2000), 27-30 August 2000, Quebec, Canada},
  pages        = {128--133},
  publisher    = {{IEEE} Computer Society},
  year         = {2000},
  url          = {https://doi.org/10.1109/PCEE.2000.873615},
  doi          = {10.1109/PCEE.2000.873615},
  timestamp    = {Thu, 23 Mar 2023 23:59:38 +0100},
  biburl       = {https://dblp.org/rec/conf/parelec/Yang00a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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