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BibTeX record conf/vlsi-dat/WuH18
@inproceedings{DBLP:conf/vlsi-dat/WuH18, author = {Yu{-}Yi Wu and Shih{-}Hsu Huang}, title = {TSV-aware 3D test wrapper chain optimization}, booktitle = {2018 International Symposium on {VLSI} Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018}, pages = {1--4}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/VLSI-DAT.2018.8373262}, doi = {10.1109/VLSI-DAT.2018.8373262}, timestamp = {Wed, 16 Oct 2019 14:14:54 +0200}, biburl = {https://dblp.org/rec/conf/vlsi-dat/WuH18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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