BibTeX record conf/vlsic/ChangNHA18

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@inproceedings{DBLP:conf/vlsic/ChangNHA18,
  author    = {Eric Chang and
               Nathan Narevsky and
               Jaeduk Han and
               Elad Alon},
  title     = {An Automated SerDes Frontend Generator Verified with a 16NM Instance
               Achieving 15 {GB/S} at 1.96 PJ/Bit},
  booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
               18-22, 2018},
  pages     = {153--154},
  year      = {2018},
  crossref  = {DBLP:conf/vlsic/2018},
  url       = {https://doi.org/10.1109/VLSIC.2018.8502313},
  doi       = {10.1109/VLSIC.2018.8502313},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsic/ChangNHA18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsic/2018,
  title     = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
               18-22, 2018},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8484863/proceeding},
  isbn      = {978-1-5386-4214-6},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsic/2018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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