BibTeX record journals/ijcse/WangSWZCF18

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@article{DBLP:journals/ijcse/WangSWZCF18,
  author       = {Xiaojun Wang and
                  Feng Shi and
                  Yizhuo Wang and
                  Hong Zhang and
                  Xu Chen and
                  Wen{-}Fei Fu},
  title        = {Power-aware high level evaluation model of interconnect length of
                  on-chip memory network topology},
  journal      = {Int. J. Comput. Sci. Eng.},
  volume       = {17},
  number       = {4},
  pages        = {422--431},
  year         = {2018},
  url          = {https://doi.org/10.1504/IJCSE.2018.096030},
  doi          = {10.1504/IJCSE.2018.096030},
  timestamp    = {Tue, 20 Oct 2020 14:11:37 +0200},
  biburl       = {https://dblp.org/rec/journals/ijcse/WangSWZCF18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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